Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: Add support for CPUFREQ-HW and CPUFREQ-HW-DEBUG for NEO

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Add cpu frequency node to be able to scale the CPU frequency.
Also add support for CPUFREQ-HW-DEBUG node to dump the EPSS registers
for debugging.

Change-Id: I5d6ebe5aa10d3421265e2a1220e1685a40c5a98b
This commit is contained in:
Kalpak Kawadkar
2021-12-11 11:21:38 +05:30
parent abdc056bae
commit ca1b029df2
2 changed files with 27 additions and 1 deletions
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4
qcom/neo-rumi.dtsi
View File

@@ -125,3 +125,7 @@
&debugcc {
clocks = <&bi_tcxo>;
};
&cpufreq_hw {
clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>;
};

24
qcom/neo.dtsi
View File

@@ -20,7 +20,7 @@
#size-cells = <2>;
chosen: chosen {
bootargs = " rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off console=ttyMSM0,115200,n8 loglevel=8";
bootargs = " rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off console=ttyMSM0,115200,n8 loglevel=8 cpufreq.default_governor=performance";
};
memory { device_type = "memory"; reg = <0 0 0 0>; };
@@ -50,6 +50,7 @@
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -73,6 +74,7 @@
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -96,6 +98,7 @@
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -119,6 +122,7 @@
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -587,6 +591,24 @@
#reset-cells = <1>;
};
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-hw-epss";
reg = <0x17d91000 0x1000>;
reg-names = "freq-domain0";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
qcom,lut-row-size = <4>;
qcom,skip-enable-check;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int";
#freq-domain-cells = <2>;
};
qcom,cpufreq-hw-debug {
compatible = "qcom,cpufreq-hw-epss-debug";
qcom,freq-hw-domain = <&cpufreq_hw 0>;
};
sdhc1_opp_table: sdhc1-opp-table {
compatible = "operating-points-v2";