mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
Merge "ARM: dts: msm: Add initial DCVS devices for anorak"
This commit is contained in:
qctecmdr
committed by
Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
commit
cb2eaa17be
314
qcom/anorak.dtsi
314
qcom/anorak.dtsi
@@ -326,6 +326,12 @@
|
||||
apps_bcm_voter: bcm_voter {
|
||||
compatible = "qcom,bcm-voter";
|
||||
};
|
||||
|
||||
dcvs_fp: qcom,dcvs-fp {
|
||||
compatible = "qcom,dcvs-fp";
|
||||
qcom,ddr-bcm-name = "MC3";
|
||||
qcom,llcc-bcm-name = "SH5";
|
||||
};
|
||||
};
|
||||
|
||||
disp_rsc_0: rsc@af20000 {
|
||||
@@ -942,6 +948,314 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
llcc_pmu: llcc-pmu@19095000 {
|
||||
compatible = "qcom,llcc-pmu-ver2";
|
||||
reg = <0x19095000 0x300>;
|
||||
reg-names = "lagg-base";
|
||||
};
|
||||
|
||||
qcom_pmu: qcom,pmu {
|
||||
compatible = "qcom,pmu";
|
||||
qcom,pmu-events-tbl =
|
||||
< 0x0008 0x3F 0xFF 0x02 >,
|
||||
< 0x0011 0x3F 0xFF 0x00 >,
|
||||
< 0x0017 0x3F 0xFF 0xFF >,
|
||||
< 0x0018 0x3F 0xFF 0xFF >,
|
||||
< 0x002A 0x3F 0xFF 0xFF >,
|
||||
< 0x002B 0x3F 0xFF 0xFF >,
|
||||
< 0x4005 0x3F 0xFF 0xFF >,
|
||||
< 0x1000 0x3F 0xFF 0xFF >;
|
||||
};
|
||||
|
||||
ddr_freq_table: ddr-freq-table {
|
||||
qcom,freq-tbl =
|
||||
< 547200 >,
|
||||
< 681600 >,
|
||||
< 768000 >,
|
||||
< 1555200 >,
|
||||
< 1708800 >,
|
||||
< 2092800 >,
|
||||
< 2736000 >,
|
||||
< 3196800 >;
|
||||
};
|
||||
|
||||
llcc_freq_table: llcc-freq-table {
|
||||
qcom,freq-tbl =
|
||||
< 300000 >,
|
||||
< 466000 >,
|
||||
< 600000 >,
|
||||
< 806000 >,
|
||||
< 933000 >,
|
||||
< 1066000 >;
|
||||
};
|
||||
|
||||
ddrqos_freq_table: ddrqos-freq-table {
|
||||
qcom,freq-tbl =
|
||||
< 0 >,
|
||||
< 1 >;
|
||||
};
|
||||
|
||||
qcom_dcvs: qcom,dcvs {
|
||||
compatible = "qcom,dcvs";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
qcom_l3_dcvs_hw: l3 {
|
||||
compatible = "qcom,dcvs-hw";
|
||||
qcom,dcvs-hw-type = <2>;
|
||||
qcom,bus-width = <32>;
|
||||
reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>;
|
||||
reg-names = "l3-base", "l3tbl-base";
|
||||
|
||||
l3_dcvs_sp: sp {
|
||||
compatible = "qcom,dcvs-path";
|
||||
qcom,dcvs-path-type = <0>;
|
||||
qcom,shared-offset = <0x0090>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom_ddr_dcvs_hw: ddr {
|
||||
compatible = "qcom,dcvs-hw";
|
||||
qcom,dcvs-hw-type = <0>;
|
||||
qcom,bus-width = <4>;
|
||||
qcom,freq-tbl = <&ddr_freq_table>;
|
||||
|
||||
ddr_dcvs_sp: sp {
|
||||
compatible = "qcom,dcvs-path";
|
||||
qcom,dcvs-path-type = <0>;
|
||||
interconnects = <&mc_virt MASTER_LLCC
|
||||
&mc_virt SLAVE_EBI1>;
|
||||
};
|
||||
|
||||
ddr_dcvs_fp: fp {
|
||||
compatible = "qcom,dcvs-path";
|
||||
qcom,dcvs-path-type = <1>;
|
||||
qcom,fp-voter = <&dcvs_fp>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
qcom_llcc_dcvs_hw: llcc {
|
||||
compatible = "qcom,dcvs-hw";
|
||||
qcom,dcvs-hw-type = <1>;
|
||||
qcom,bus-width = <16>;
|
||||
qcom,freq-tbl = <&llcc_freq_table>;
|
||||
|
||||
llcc_dcvs_sp: sp {
|
||||
compatible = "qcom,dcvs-path";
|
||||
qcom,dcvs-path-type = <0>;
|
||||
interconnects = <&gem_noc MASTER_APPSS_PROC
|
||||
&gem_noc SLAVE_LLCC>;
|
||||
};
|
||||
|
||||
llcc_dcvs_fp: fp {
|
||||
compatible = "qcom,dcvs-path";
|
||||
qcom,dcvs-path-type = <1>;
|
||||
qcom,fp-voter = <&dcvs_fp>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
qcom_ddrqos_dcvs_hw: ddrqos {
|
||||
compatible = "qcom,dcvs-hw";
|
||||
qcom,dcvs-hw-type = <3>;
|
||||
qcom,bus-width = <1>;
|
||||
qcom,freq-tbl = <&ddrqos_freq_table>;
|
||||
|
||||
ddrqos_dcvs_sp: sp {
|
||||
compatible = "qcom,dcvs-path";
|
||||
qcom,dcvs-path-type = <0>;
|
||||
interconnects = <&mc_virt MASTER_LLCC
|
||||
&mc_virt SLAVE_EBI1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qcom_memlat: qcom,memlat {
|
||||
compatible = "qcom,memlat";
|
||||
qcom,be-stall-ev = <0x4005>;
|
||||
ddr {
|
||||
compatible = "qcom,memlat-grp";
|
||||
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
|
||||
qcom,sampling-path = <&ddr_dcvs_fp>;
|
||||
qcom,miss-ev = <0x1000>;
|
||||
|
||||
gold {
|
||||
compatible = "qcom,memlat-mon";
|
||||
qcom,cpulist = <&CPU0 &CPU1>;
|
||||
qcom,sampling-enabled;
|
||||
qcom,cpufreq-memfreq-tbl =
|
||||
< 960000 547000 >,
|
||||
< 1228800 768000 >,
|
||||
< 1651200 1555000 >,
|
||||
< 1920000 1708000 >,
|
||||
< 2361600 2092000 >;
|
||||
};
|
||||
|
||||
prime {
|
||||
compatible = "qcom,memlat-mon";
|
||||
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
|
||||
qcom,sampling-enabled;
|
||||
qcom,cpufreq-memfreq-tbl =
|
||||
< 960000 547000 >,
|
||||
< 1228800 768000 >,
|
||||
< 1651200 1555000 >,
|
||||
< 1920000 1708000 >,
|
||||
< 2361600 2092000 >;
|
||||
};
|
||||
|
||||
gold-compute {
|
||||
compatible = "qcom,memlat-mon";
|
||||
qcom,cpulist = <&CPU0 &CPU1>;
|
||||
qcom,sampling-enabled;
|
||||
qcom,compute-mon;
|
||||
qcom,cpufreq-memfreq-tbl =
|
||||
< 1228800 547000 >,
|
||||
< 1516800 768000 >,
|
||||
< 1651200 1555000 >,
|
||||
< 1920000 1708000 >,
|
||||
< 2361600 2092000 >;
|
||||
};
|
||||
|
||||
prime-compute {
|
||||
compatible = "qcom,memlat-mon";
|
||||
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
|
||||
qcom,sampling-enabled;
|
||||
qcom,compute-mon;
|
||||
qcom,cpufreq-memfreq-tbl =
|
||||
< 1228800 547000 >,
|
||||
< 1516800 768000 >,
|
||||
< 1651200 1555000 >,
|
||||
< 1920000 1708000 >,
|
||||
< 2361600 2092000 >;
|
||||
};
|
||||
};
|
||||
|
||||
llcc {
|
||||
compatible = "qcom,memlat-grp";
|
||||
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
|
||||
qcom,sampling-path = <&llcc_dcvs_fp>;
|
||||
qcom,miss-ev = <0x2A>;
|
||||
|
||||
gold {
|
||||
compatible = "qcom,memlat-mon";
|
||||
qcom,cpulist = <&CPU0 &CPU1>;
|
||||
qcom,cpufreq-memfreq-tbl =
|
||||
< 691200 300000 >,
|
||||
< 960000 466000 >,
|
||||
< 1228800 600000 >,
|
||||
< 1651200 806000 >,
|
||||
< 2361600 933000 >;
|
||||
qcom,sampling-enabled;
|
||||
};
|
||||
|
||||
prime {
|
||||
compatible = "qcom,memlat-mon";
|
||||
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
|
||||
qcom,cpufreq-memfreq-tbl =
|
||||
< 691200 300000 >,
|
||||
< 960000 466000 >,
|
||||
< 1228800 600000 >,
|
||||
< 1651200 806000 >,
|
||||
< 2361600 933000 >;
|
||||
qcom,sampling-enabled;
|
||||
};
|
||||
};
|
||||
|
||||
l3 {
|
||||
compatible = "qcom,memlat-grp";
|
||||
qcom,target-dev = <&qcom_l3_dcvs_hw>;
|
||||
qcom,sampling-path = <&l3_dcvs_sp>;
|
||||
qcom,miss-ev = <0x17>;
|
||||
qcom,wb-ev = <0x18>;
|
||||
qcom,access-ev = <0x2B>;
|
||||
|
||||
gold {
|
||||
compatible = "qcom,memlat-mon";
|
||||
qcom,cpulist = <&CPU0 &CPU1>;
|
||||
qcom,cpufreq-memfreq-tbl =
|
||||
< 300000 300000 >,
|
||||
< 691200 428400 >,
|
||||
< 960000 556800 >,
|
||||
< 1094400 691200 >,
|
||||
< 1228800 825600 >,
|
||||
< 1372800 940800 >,
|
||||
< 1516800 1075200 >,
|
||||
< 1651200 1209600 >,
|
||||
< 1920000 1305600 >,
|
||||
< 2054400 1401600 >,
|
||||
< 2361600 1507200 >;
|
||||
qcom,sampling-enabled;
|
||||
};
|
||||
|
||||
prime {
|
||||
compatible = "qcom,memlat-mon";
|
||||
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
|
||||
qcom,cpufreq-memfreq-tbl =
|
||||
< 300000 300000 >,
|
||||
< 691200 428400 >,
|
||||
< 960000 556800 >,
|
||||
< 1094400 691200 >,
|
||||
< 1228800 825600 >,
|
||||
< 1372800 940800 >,
|
||||
< 1516800 1075200 >,
|
||||
< 1651200 1209600 >,
|
||||
< 1920000 1305600 >,
|
||||
< 2054400 1401600 >,
|
||||
< 2361600 1507200 >;
|
||||
qcom,sampling-enabled;
|
||||
};
|
||||
|
||||
prime-compute {
|
||||
compatible = "qcom,memlat-mon";
|
||||
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
|
||||
qcom,cpufreq-memfreq-tbl =
|
||||
< 1977600 307200 >,
|
||||
< 2707200 1344000 >;
|
||||
qcom,sampling-enabled;
|
||||
qcom,compute-mon;
|
||||
};
|
||||
};
|
||||
|
||||
ddrqos {
|
||||
compatible = "qcom,memlat-grp";
|
||||
qcom,target-dev = <&qcom_ddrqos_dcvs_hw>;
|
||||
qcom,sampling-path = <&ddrqos_dcvs_sp>;
|
||||
qcom,miss-ev = <0x1000>;
|
||||
ddrqos_prime_latfloor: prime-latfloor {
|
||||
compatible = "qcom,memlat-mon";
|
||||
qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
|
||||
qcom,cpufreq-memfreq-tbl =
|
||||
< 1881600 0 >,
|
||||
< 2707200 1 >;
|
||||
qcom,sampling-enabled;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
bwmon_llcc: qcom,bwmon-llcc@190b6400 {
|
||||
compatible = "qcom,bwmon4";
|
||||
reg = <0x190b6400 0x300>, <0x190b6300 0x200>;
|
||||
reg-names = "base", "global_base";
|
||||
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,mport = <0>;
|
||||
qcom,hw-timer-hz = <19200000>;
|
||||
qcom,count-unit = <0x10000>;
|
||||
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
|
||||
};
|
||||
|
||||
bwmon_ddr: qcom,bwmon-ddr@19091000 {
|
||||
compatible = "qcom,bwmon5";
|
||||
reg = <0x19091000 0x1000>;
|
||||
reg-names = "base";
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,hw-timer-hz = <19200000>;
|
||||
qcom,count-unit = <0x10000>;
|
||||
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
|
||||
};
|
||||
|
||||
ipcc_mproc: qcom,ipcc@ed18000 {
|
||||
compatible = "qcom,ipcc";
|
||||
reg = <0x408000 0x1000>;
|
||||
|
||||
Reference in New Issue
Block a user