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ARM: dts: msm: Add PCIe PHY, PARF and DBI status registers for Hang event

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Add list of PCIe PHY, PARF, DBI status registers for Hang event for
both RC0 and RC1 for Wapio.

Change-Id: I7c15daa1f502d79b65468d24915f4b8540be0b46
This commit is contained in:
Krishna chaitanya Chundru
2021-12-20 10:52:33 +05:30
committed by Gerrit - the friendly Code Review server
parent c42bc05fd3
commit ce712be20e
2 changed files with 48 additions and 0 deletions
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15
bindings/pci/pci-msm.txt
View File

@@ -392,6 +392,21 @@ interconnects:
Definition: Enable to notify the client driver for recovery when
config space is not accessible
- qcom,parf-debug-reg:
Usage: optional
value type: <u32>
Definition: Offset from PCIe parf base to dump pcie parf status registers
- qcom,dbi-debug-reg:
Usage: optional
value type: <u32>
Definition: Offset from PCIe DBI base to dump pcie DBI status registers
- qcom,phy-debug-reg:
Usage: optional
value type: <u32>
Definition: Offset from PCIe PHY base to dump pcie phy status registers
==============
Root port node
==============

33
qcom/waipio-pcie.dtsi
View File

@@ -206,6 +206,23 @@
0x0200 0x00 0x0
0x0244 0x03 0x0>;
qcom,parf-debug-reg = <0x01B0 0x0024 0x0028 0x0224 0x0500
0x04D0 0x04D4 0x03C0 0x0630 0x0230
0x0000>;
qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x0204 0x0730
0x0734 0x0738 0x073C>;
qcom,phy-debug-reg = <0x0068 0x0140 0x0144 0x0148 0x014C
0x0150 0x0160 0x0178 0x0ED0 0x0EDC
0x0F34 0x0F38 0x0f3C 0x0F40 0x0F44
0x0F48 0x0F4C 0x0F50 0x0F54 0x0F58
0x11E8 0x0A00 0x0A04 0x0A08 0x0A0C
0x0A10 0x0A14 0x0A18 0x0C20 0x0214
0x0218 0x021C 0x0220 0x0224 0x0228
0x022C 0x0230 0x0234 0x0238 0x023C
0x0600 0x0604 0x1204 0x1210>;
pcie0_rp: pcie0_rp {
reg = <0 0 0 0 0>;
};
@@ -529,6 +546,22 @@
0x1200 0x00 0x0
0x1244 0x03 0x0>;
qcom,parf-debug-reg = <0x01B0 0x0024 0x0028 0x0224 0x0500
0x04D0 0x04D4 0x03C0 0x0630 0x0230
0x0000>;
qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x0204 0x0730
0x0734 0x0738 0x073C>;
qcom,phy-debug-reg = <0x1068 0x1140 0x1144 0x1148 0x114C
0x1150 0x1160 0x1178 0x00b8 0x08B8
0x00C4 0x08C4 0x0478 0x0C78 0x1800
0x1C00 0x1804 0x1C04 0x1808 0x1C08
0x180C 0x1C0C 0x1810 0x1C10 0x1814
0x1C14 0x1818 0x1C18 0x1A20 0x1E20
0x1214 0x1218 0x121C 0x1220 0x1224
0x1228 0x122C 0x1230 0x1234 0x1238
0x123C 0x1400 0x1404>;
pcie1_rp: pcie1_rp {
reg = <0 0 0 0 0>;
};