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https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: qcom: Add cnss2 node for Anorak(ATP) + HMT support
Add initial support for HMT for anorak(ATP). Change-Id: Ib4415a2d0809671aef7d813974a210116da46897 CRs-Fixed: 3371285
This commit is contained in:
Anuj Khera
@@ -3,6 +3,7 @@
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#include <dt-bindings/clock/qcom,gcc-anorak.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include "anorak-pmic-overlay.dtsi"
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#include <dt-bindings/interconnect/qcom,anorak.h>
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&soc {
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gpio_keys {
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@@ -156,3 +157,146 @@
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status = "ok";
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};
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&wlan {
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status = "disabled";
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};
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&bluetooth {
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status = "disabled";
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};
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&cnss_pins {
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cnss_host_sol_default: cnss_host_sol_default {
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mux {
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pins = "gpio124";
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function = "gpio";
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};
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config {
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pins = "gpio124";
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drive-strength = <4>;
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bias-pull-down;
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};
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};
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cnss_dev_sol_default: cnss_dev_sol_default {
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mux {
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pins = "gpio123";
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function = "gpio";
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};
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config {
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pins = "gpio123";
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drive-strength = <4>;
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bias-pull-down;
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};
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};
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};
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&soc {
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wlan_kiwi: qcom,cnss-kiwi@b0000000 {
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compatible = "qcom,cnss-kiwi";
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reg = <0xb0000000 0x10000>;
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reg-names = "smmu_iova_ipa";
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wlan-en-gpio = <&tlmm 120 0>;
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wlan-host-sol-gpio = <&tlmm 124 0>;
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wlan-dev-sol-gpio = <&tlmm 123 0>;
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pinctrl-names = "wlan_en_active", "wlan_en_sleep", "sol_default";
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pinctrl-0 = <&cnss_wlan_en_active>;
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pinctrl-1 = <&cnss_wlan_en_sleep>;
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pinctrl-2 = <&cnss_host_sol_default &cnss_dev_sol_default>;
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qcom,wlan;
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qcom,wlan-rc-num = <0>;
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qcom,wlan-ramdump-dynamic = <0x780000>;
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qcom,wlan-cbc-enabled;
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use-pm-domain;
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qcom,same-dt-multi-dev;
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mboxes = <&qmp_aop 0>;
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vdd-wlan-dig-supply = <&S3B>;
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qcom,vdd-wlan-dig-config = <950000 1120000 0 0 1>;
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vdd-wlan-io-supply = <&L7B>;
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qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
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vdd-wlan-rfa1-supply = <&S1B>;
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qcom,vdd-wlan-rfa1-config = <1880000 2040000 0 0 1>;
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vdd-wlan-rfa2-supply = <&S2B>;
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qcom,vdd-wlan-rfa2-config = <1352000 1370000 0 0 1>;
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vdd-wlan-supply = <&S4F>;
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qcom,vdd-wlan-config = <952000 952000 0 0 1>;
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interconnects =
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<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
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<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
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interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";
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qcom,icc-path-count = <2>;
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qcom,bus-bw-cfg-count = <9>;
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qcom,bus-bw-cfg =
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/** ICC Path 1 **/
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<0 0>, /* no vote */
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/* idle: 0-18 Mbps snoc/anoc: 150 Mhz */
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<2250 1599540>,
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/* low: 18-60 Mbps snoc/anoc: 150 Mhz */
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<7500 1599540>,
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/* medium: 60-240 Mbps snoc/anoc: 150 Mhz*/
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<30000 1599540>,
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/* high: 240-1200 Mbps snoc/anoc: 240 Mhz */
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<100000 3199610>,
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/* very high: > 1200 Mbps snoc/anoc: 403 Mhz */
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<175000 6447980>,
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/* ultra high: DBS mode snoc/anoc: 403 Mhz */
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<175000 6447980>,
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/* super high: DBS mode snoc/anoc: 403 Mhz */
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<175000 6447980>,
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/* low (latency critical): 18-60 Mbps snoc/anoc: 240 Mhz */
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<7500 3199610>,
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/** ICC Path 2 **/
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<0 0>,
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/* ddr: 451.2 MHz */
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<2250 2749600>,
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/* ddr: 451.2 MHz */
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<7500 2749600>,
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/* ddr: 451.2 MHz */
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<30000 2749600>,
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/* ddr: 451.2 MHz */
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<100000 2749600>,
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/* ddr: 1555 MHz */
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<175000 9479200>,
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/* ddr: 2092 MHz */
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<175000 12756000>,
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/* ddr: 2133 MHz */
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<175000 13106400>,
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/* ddr: 547.2 MHz */
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<7500 3335200>;
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};
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bt_hmt: bt_kiwi {
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compatible = "qcom,kiwi";
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pinctrl-names = "default";
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pinctrl-0 = <&bt_en_sleep>;
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qcom,wl-reset-gpio = <&tlmm 120 0>; /* WL_CTRL */
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qcom,bt-reset-gpio = <&tlmm 122 0>; /* BT_EN */
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qcom,bt-sw-ctrl-gpio = <&tlmm 146 0>; /* SW_CTRL */
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qcom,bt-vdd-io-supply = <&L7B>; /* BT VDD1.8 AON */
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qcom,bt-vdd-aon-supply = <&S3B>; /* BT AON LDO*/
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qcom,bt-vdd-rfacmn-supply = <&S3B>;
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qcom,bt-vdd-dig-supply = <&S3B>; /* BT LDO*/
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qcom,bt-vdd-rfa-0p8-supply = <&S3B>; /* BT RFA0p8 CMN LDO*/
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qcom,bt-vdd-rfa1-supply = <&S1B>; /* BT RFA1.8 LDO */
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qcom,bt-vdd-rfa2-supply = <&S2B>; /* BT RFA1.2 LDO */
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qcom,bt-vdd-io-config = <1800000 1800000 0 1>;
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qcom,bt-vdd-aon-config = <950000 950000 0 1>;
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qcom,bt-vdd-rfacmn-config = <950000 950000 0 1>;
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qcom,bt-vdd-dig-config = <950000 950000 0 1>;
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qcom,bt-vdd-rfa-0p8-config = <950000 950000 0 1>;
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qcom,bt-vdd-rfa1-config = <1900000 1900000 0 1>;
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qcom,bt-vdd-rfa2-config = <1350000 1350000 0 1>;
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};
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};
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