ARM: dts: msm: Update DISPCC and debugCC clock nodes for SHIMA

Update clock node and GDSC of DISPCC and debugCC for SHIMA.

Change-Id: I5891f471b19ed50ace260ca698c5b02f0f8cad77
This commit is contained in:
Jagadeesh Kona
2020-07-17 07:28:51 +05:30
parent 4f74c2bfda
commit cfd3c1ffff
3 changed files with 28 additions and 4 deletions

View File

@@ -145,7 +145,7 @@
/* GDSCs in DISPCC */
disp_cc_mdss_core_gdsc: qcom,gdsc@af03000 {
compatible = "regulator-fixed";
compatible = "qcom,gdsc";
reg = <0xaf03000 0x4>;
regulator-name = "disp_cc_mdss_core_gdsc";
proxy-supply = <&disp_cc_mdss_core_gdsc>;

View File

@@ -170,3 +170,8 @@
clocks = <&bi_tcxo>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>;
};
&dispcc {
clocks = <&bi_tcxo>, <&bi_tcxo_ao>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>, <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
};

View File

@@ -690,9 +690,15 @@
#reset-cells = <1>;
};
dispcc: qcom,dispcc@af00000 {
compatible = "qcom,dummycc";
clock-output-names = "dispcc_clocks";
dispcc: clock-controller@af00000 {
compatible = "qcom,shima-dispcc", "syscon";
reg = <0xaf00000 0x20000>;
reg-names = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>, <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "gcc_disp_gpll0_clk_src",
"sleep_clk", "cfg_ahb";
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -724,12 +730,25 @@
#reset-cells = <1>;
};
apsscc: syscon@182a0000 {
compatible = "syscon";
reg = <0x182a0000 0x1c>;
};
mccc: syscon@90ba000 {
compatible = "syscon";
reg = <0x90ba000 0x54>;
};
debugcc: debug-clock-controller@0 {
compatible = "qcom,shima-debugcc";
qcom,gcc = <&gcc>;
qcom,videocc = <&videocc>;
qcom,camcc = <&camcc>;
qcom,dispcc = <&dispcc>;
qcom,gpucc = <&gpucc>;
qcom,apsscc = <&apsscc>;
qcom,mccc = <&mccc>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo_clk_src";
#clock-cells = <1>;