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https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
ARM: dts: msm: Update DISPCC and debugCC clock nodes for SHIMA
Update clock node and GDSC of DISPCC and debugCC for SHIMA. Change-Id: I5891f471b19ed50ace260ca698c5b02f0f8cad77
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@@ -145,7 +145,7 @@
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/* GDSCs in DISPCC */
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disp_cc_mdss_core_gdsc: qcom,gdsc@af03000 {
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compatible = "regulator-fixed";
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compatible = "qcom,gdsc";
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reg = <0xaf03000 0x4>;
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regulator-name = "disp_cc_mdss_core_gdsc";
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proxy-supply = <&disp_cc_mdss_core_gdsc>;
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@@ -170,3 +170,8 @@
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clocks = <&bi_tcxo>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>, <&gcc GCC_GPU_CFG_AHB_CLK>;
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};
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&dispcc {
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clocks = <&bi_tcxo>, <&bi_tcxo_ao>,
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<&gcc GCC_DISP_GPLL0_CLK_SRC>, <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
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};
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@@ -690,9 +690,15 @@
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#reset-cells = <1>;
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};
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dispcc: qcom,dispcc@af00000 {
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compatible = "qcom,dummycc";
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clock-output-names = "dispcc_clocks";
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dispcc: clock-controller@af00000 {
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compatible = "qcom,shima-dispcc", "syscon";
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reg = <0xaf00000 0x20000>;
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reg-names = "cc_base";
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vdd_cx-supply = <&VDD_CX_LEVEL>;
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
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<&gcc GCC_DISP_GPLL0_CLK_SRC>, <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
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clock-names = "bi_tcxo", "bi_tcxo_ao", "gcc_disp_gpll0_clk_src",
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"sleep_clk", "cfg_ahb";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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@@ -724,12 +730,25 @@
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#reset-cells = <1>;
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};
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apsscc: syscon@182a0000 {
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compatible = "syscon";
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reg = <0x182a0000 0x1c>;
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};
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mccc: syscon@90ba000 {
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compatible = "syscon";
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reg = <0x90ba000 0x54>;
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};
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debugcc: debug-clock-controller@0 {
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compatible = "qcom,shima-debugcc";
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qcom,gcc = <&gcc>;
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qcom,videocc = <&videocc>;
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qcom,camcc = <&camcc>;
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qcom,dispcc = <&dispcc>;
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qcom,gpucc = <&gpucc>;
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qcom,apsscc = <&apsscc>;
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qcom,mccc = <&mccc>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "xo_clk_src";
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#clock-cells = <1>;
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