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dt-bindings: interconnect: add interconnect bindings

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Add interconnect device bindings. These devices can be used
to describe any RPMH and NoC based interconnect devices.

Change-Id: Ic490e7a88f3d74f169ebad8b3b8884c3ac3e4d8d
This commit is contained in:
Odelu Kukatla
2020-02-17 21:42:12 +05:30
parent 9fbf9f5f31
commit d0cb180085
2 changed files with 34 additions and 1 deletions
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4
bindings/interconnect/qcom,epss-l3.txt
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@@ -7,7 +7,9 @@ performance states of the CPU subsystem.
Required properties :
- compatible : shall contain only one of the following:
"qcom,lahaina-epss-l3-shared",
"qcom,lahaina-epss-l3-cpu";
"qcom,lahaina-epss-l3-cpu",
"qcom,shima-epss-l3-cpu",
"qcom,shima-epss-l3-shared";
- reg : Address and length of the register set for the device
- clock-names: should contain "xo", "alternate"
- clocks: list of phandle and clock specifier pairs corresponding to

31
bindings/interconnect/qcom,shima.txt Normal file
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@@ -0,0 +1,31 @@
Qualcomm Technologies, Inc. Shima Network-On-Chip interconnect driver binding
-----------------------------------------------------------
Shima interconnect providers support system bandwidth requirements through
RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
able to communicate with the BCM through the Resource State Coordinator (RSC)
associated with each execution environment. Provider nodes must point to at
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
Required properties :
- compatible : shall contain only one of the following:
"qcom,shima-aggre1_noc",
"qcom,shima-aggre2_noc",
"qcom,shima-clk_virt",
"qcom,shima-config_noc",
"qcom,shima-dc_noc",
"qcom,shima-gem_noc",
"qcom,shima-lpass_ag_noc",
"qcom,shima-mc_virt",
"qcom,shima-mmss_noc",
"qcom,shima-nsp_noc",
"qcom,shima-system_noc",
- #interconnect-cells : should contain 1
Examples:
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,shima-aggre1_noc";
interconnect-cells = <1>;
};