Merge "ARM: dts: msm: Add dynamic power coefficient and efficiency for Neo"

This commit is contained in:
qctecmdr
2022-02-07 21:18:52 -08:00
committed by Gerrit - the friendly Code Review server

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@@ -47,6 +47,8 @@
cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -68,6 +70,8 @@
cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -89,6 +93,8 @@
cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -110,6 +116,8 @@
cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;