Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
2
0
Fork 0
mirror of https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees synced 2026-02-01 08:51:30 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge "ARM: dts: msm: Update the freq domain max core count for all CPUs"

Browse Source
This commit is contained in:
qctecmdr
2022-12-13 21:34:08 -08:00
committed by Gerrit - the friendly Code Review server
parent fcb1ccde6b b1a97170bf
commit d67c274a2b
1 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
qcom/ravelin.dtsi
View File

@@ -79,7 +79,7 @@
cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 6>;
qcom,freq-domain = <&cpufreq_hw 0 8>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
L2_0: l2-cache {
@@ -104,7 +104,7 @@
cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 6>;
qcom,freq-domain = <&cpufreq_hw 0 8>;
next-level-cache = <&L2_1>;
#cooling-cells = <2>;
L2_1: l2-cache {
@@ -124,7 +124,7 @@
cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 6>;
qcom,freq-domain = <&cpufreq_hw 0 8>;
next-level-cache = <&L2_2>;
#cooling-cells = <2>;
L2_2: l2-cache {
@@ -144,7 +144,7 @@
cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 6>;
qcom,freq-domain = <&cpufreq_hw 0 8>;
next-level-cache = <&L2_3>;
#cooling-cells = <2>;
L2_3: l2-cache {
@@ -166,7 +166,7 @@
power-domain-names = "psci";
next-level-cache = <&L2_4>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0 6>;
qcom,freq-domain = <&cpufreq_hw 0 8>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
@@ -184,7 +184,7 @@
cpu-idle-states = <&SILVER_CPU_OFF &SILVER_CPU_RAIL_OFF>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 6>;
qcom,freq-domain = <&cpufreq_hw 0 8>;
next-level-cache = <&L2_5>;
#cooling-cells = <2>;
L2_5: l2-cache {
@@ -204,7 +204,7 @@
cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1 2>;
qcom,freq-domain = <&cpufreq_hw 1 8>;
next-level-cache = <&L2_6>;
#cooling-cells = <2>;
L2_6: l2-cache {
@@ -224,7 +224,7 @@
cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1 2>;
qcom,freq-domain = <&cpufreq_hw 1 8>;
next-level-cache = <&L2_7>;
#cooling-cells = <2>;
L2_7: l2-cache {