Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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Merge "ARM: dts: msm: add capacity and DPC properties for Lahaina"

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qctecmdr
2019-10-03 13:17:48 -07:00
committed by Gerrit - the friendly Code Review server
parent 45956dc8e2 1a49d0914f
commit de84d0016f
1 changed files with 16 additions and 0 deletions
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qcom/lahaina.dtsi
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@@ -35,6 +35,8 @@
enable-method = "spin-table";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
@@ -57,6 +59,8 @@
enable-method = "spin-table";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
@@ -73,6 +77,8 @@
enable-method = "spin-table";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
@@ -89,6 +95,8 @@
enable-method = "spin-table";
cache-size = <0x8000>;
cpu-release-addr = <0x0 0x90000000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
@@ -105,6 +113,8 @@
enable-method = "spin-table";
cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <454>;
next-level-cache = <&L2_4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
@@ -121,6 +131,8 @@
enable-method = "spin-table";
cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <454>;
next-level-cache = <&L2_5>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
@@ -137,6 +149,8 @@
enable-method = "spin-table";
cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <454>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
@@ -153,6 +167,8 @@
enable-method = "spin-table";
cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
capacity-dmips-mhz = <2048>;
dynamic-power-coefficient = <704>;
next-level-cache = <&L2_7>;
L2_7: l2-cache {
compatible = "arm,arch-cache";