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Merge "ARM: dts: msm: Add QUPV3 SE dt node for uart on Lahaina"

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qctecmdr
2019-10-31 10:44:52 -07:00
committed by Gerrit - the friendly Code Review server
parent 1f6ea26173 720a225aec
commit decbd9cc70
3 changed files with 108 additions and 0 deletions
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56
qcom/lahaina-pinctrl.dtsi
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@@ -8,6 +8,62 @@
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
qupv3_se3_2uart_pins: qupv3_se3_2uart_pins {
qupv3_se3_2uart_active: qupv3_se3_2uart_active {
mux {
pins = "gpio18", "gpio19";
function = "qup3";
};
config {
pins = "gpio18", "gpio19";
drive-strength = <2>;
bias-disable;
};
};
qupv3_se3_2uart_sleep: qupv3_se3_2uart_sleep {
mux {
pins = "gpio18", "gpio19";
function = "gpio";
};
config {
pins = "gpio18", "gpio19";
drive-strength = <2>;
bias-disable;
};
};
};
qupv3_se2_2uart_pins: qupv3_se2_2uart_pins {
qupv3_se2_2uart_active: qupv3_se2_2uart_active {
mux {
pins = "gpio14", "gpio15";
function = "qup2";
};
config {
pins = "gpio14", "gpio15";
drive-strength = <2>;
bias-disable;
};
};
qupv3_se2_2uart_sleep: qupv3_se2_2uart_sleep {
mux {
pins = "gpio14", "gpio15";
function = "gpio";
};
config {
pins = "gpio14", "gpio15";
drive-strength = <2>;
bias-disable;
};
};
};
};
cam_sensor_mclk0_active: cam_sensor_mclk0_active {

50
qcom/lahaina-qupv3.dtsi Normal file
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@@ -0,0 +1,50 @@
#include <dt-bindings/interconnect/qcom,lahaina.h>
&soc {
/* QUPv3 West instances */
qupv3_0: qcom,qupv3_0_geni_se@0x9C0000 {
compatible = "qcom,qupv3-geni-se";
reg = <0x9C0000 0x2000>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-bus-ids =
<MASTER_QUP_0 SLAVE_EBI1>;
iommus = <&apps_smmu 0x5a3 0x0>;
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
qcom,iommu-dma = "atomic";
};
/* Debug UART Instance for CDP/MTP/RUMI platform: QUPV3_0_SE3 */
qupv3_se3_2uart: qcom,qup_uart@0x98C000 {
compatible = "qcom,msm-geni-console";
reg = <0x98C000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se3_2uart_active>;
pinctrl-1 = <&qupv3_se3_2uart_sleep>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
qcom,wrapper-core = <&qupv3_0>;
status = "ok";
};
/* Debug UART Instance for CDP/MTP/RUMI platform: QUPV3_0_SE2 */
qupv3_se2_2uart: qcom,qup_uart@0x988000 {
compatible = "qcom,msm-geni-console";
reg = <0x988000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk", "m-ahb", "s-ahb";
clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&qupv3_se2_2uart_active>;
pinctrl-1 = <&qupv3_se2_2uart_sleep>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
qcom,wrapper-core = <&qupv3_0>;
status = "disabled";
};
};

2
qcom/lahaina.dtsi
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@@ -23,6 +23,7 @@
aliases {
ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
serial0 = &qupv3_se3_2uart;
};
cpus {
@@ -1597,3 +1598,4 @@
#include "msm-arm-smmu-lahaina.dtsi"
#include "lahaina-usb.dtsi"
#include "lahaina-pm.dtsi"
#include "lahaina-qupv3.dtsi"