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ARM: dts: msm: Added SSR and Debug signal in IPCLite DTSi

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Added SSR and Debug signals in IPCLite

Change-Id: I0ad87b655a8a26c9aa36b9b9dceed22449b850d5
This commit is contained in:
Kuldeep Singh
2023-05-09 15:15:18 +05:30
committed by Gerrit - the friendly Code Review server
parent 16a2037d23
commit e1cd438606
1 changed files with 80 additions and 0 deletions
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80
qcom/anorak.dtsi
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@@ -1790,6 +1790,26 @@
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_4 {
index = <4>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_5 {
index = <5>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_APSS
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
IRQ_TYPE_EDGE_RISING>;
};
};
ipclite_cdsp: cdsp {
@@ -1836,6 +1856,26 @@
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_4 {
index = <4>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_5 {
index = <5>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CDSP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
IRQ_TYPE_EDGE_RISING>;
};
};
ipclite_cvp: cvp {
@@ -1882,6 +1922,26 @@
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_4 {
index = <4>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_5 {
index = <5>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_CVP
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
IRQ_TYPE_EDGE_RISING>;
};
};
ipclite_vpu: vpu {
@@ -1928,6 +1988,26 @@
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_4 {
index = <4>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_VPU
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
IRQ_TYPE_EDGE_RISING>;
};
ipclite_signal_5 {
index = <5>;
mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
interrupt-parent = <&ipcc_compute_l0>;
interrupts = <IPCC_CLIENT_VPU
IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
IRQ_TYPE_EDGE_RISING>;
};
};
};