ARM: dts: msm: Add cvp device for shima

Add cvp device node for shima.

Change-Id: I1cb376607152f2f8c5342d6b4c038066bc080371

bindings/media/msm-cvp.txt

@@ -6,6 +6,7 @@ cvp
 Required properties:
 - compatible : one of:
 	- "qcom,msm-cvp"
+	- "qcom,shima-cvp" : Invokes driver specific data for shima.
 	- "qcom,lahaina-cvp" : Invokes driver specific data for Lahaina.
 	- "qcom,kona-cvp" : Invokes driver specific data for kona.
 

qcom/lahaina-cvp.dtsi

@@ -39,6 +39,9 @@
 		pas-id = <26>;
 		memory-region = <&pil_cvp_mem>;
 
+		/* CVP Firmware ELF image name */
+		cvp,firmware-name = "evass";
+
 		/* Buses */
 		cvp_cnoc {
 			compatible = "qcom,msm-cvp,bus";

qcom/shima-cvp.dtsi

@@ -0,0 +1,96 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/interconnect/qcom,shima.h>
+#include <dt-bindings/clock/qcom,videocc-shima.h>
+
+&soc {
+	msm_cvp: qcom,cvp@ab00000 {
+		compatible = "qcom,msm-cvp", "qcom,shima-cvp";
+		status = "ok";
+		reg = <0xab00000 0x100000>;
+		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+
+		/* Supply */
+		cvp-supply = <&video_cc_mvs1c_gdsc>;
+		cvp-core-supply = <&video_cc_mvs1_gdsc>;
+
+		/* Clocks */
+		clock-names = "gcc_video_axi1", "cvp_clk", "core_clk";
+		clocks = <&gcc GCC_VIDEO_AXI1_CLK>,
+			<&videocc VIDEO_CC_MVS1C_CLK>,
+			<&videocc VIDEO_CC_MVS1_CLK>;
+		qcom,proxy-clock-names = "gcc_video_axi1",
+			"cvp_clk", "core_clk";
+
+		qcom,clock-configs = <0x0 0x1 0x1>;
+		qcom,allowed-clock-rates = <280000000 366000000 444000000>;
+
+		resets = <&gcc GCC_VIDEO_AXI1_CLK_ARES>,
+			<&videocc VIDEO_CC_MVS1C_CLK_ARES>;
+		reset-names = "cvp_axi_reset", "cvp_core_reset";
+		reset-power-status = <0x2 0x1>;
+
+		qcom,reg-presets = <0xB0088 0x0>;
+		qcom,ipcc-reg = <0x400000 0x100000>;
+
+		/* CVP Firmware ELF image name */
+		cvp,firmware-name = "evass-lt";
+
+		/* Buses */
+		cvp_cnoc {
+			compatible = "qcom,msm-cvp,bus";
+			label = "cvp-cnoc";
+			qcom,bus-master = <MASTER_APPSS_PROC>;
+			qcom,bus-slave = <SLAVE_VENUS_CFG>;
+			qcom,bus-governor = "performance";
+			qcom,bus-range-kbps = <1000 1000>;
+		};
+
+		cvp_bus_ddr {
+			compatible = "qcom,msm-cvp,bus";
+			label = "cvp-ddr";
+			qcom,bus-master = <MASTER_VIDEO_PROC>;
+			qcom,bus-slave = <SLAVE_EBI1>;
+			qcom,bus-governor = "performance";
+			qcom,bus-range-kbps = <1000 6533000>;
+		};
+
+		/* MMUs */
+		cvp_non_secure_cb {
+			compatible = "qcom,msm-cvp,context-bank";
+			label = "cvp_hlos";
+			iommus =
+				<&apps_smmu 0x2920 0x400>;
+			buffer-types = <0xfff>;
+			dma-coherent-hint-cached;
+			qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>;
+		};
+
+
+		cvp_secure_nonpixel_cb {
+			compatible = "qcom,msm-cvp,context-bank";
+			label = "cvp_sec_nonpixel";
+			iommus =
+				<&apps_smmu 0x2924 0x400>;
+			buffer-types = <0x741>;
+			qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>;
+			qcom,iommu-vmid = <0xB>;
+		};
+
+		cvp_secure_pixel_cb {
+			compatible = "qcom,msm-cvp,context-bank";
+			label = "cvp_sec_pixel";
+			iommus =
+				<&apps_smmu 0x2923 0x400>;
+			buffer-types = <0x106>;
+			qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>;
+			qcom,iommu-vmid = <0xA>;
+		};
+
+		/* Memory Heaps */
+		qcom,msm-cvp,mem_cdsp {
+			compatible = "qcom,msm-cvp,mem-cdsp";
+			memory-region = <&cdsp_mem>;
+		};
+	};
+};

qcom/shima.dtsi

@@ -359,6 +359,14 @@
 			linux,cma-default;
 		};
 
+		cdsp_mem: cdsp_region {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x400000>;
+		};
+
 		dump_mem: mem_dump_region {
 			compatible = "shared-dma-pool";
 			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
@@ -1157,6 +1165,16 @@
 		mbox-names = "aop";
 	};
 
+	qcom,evass@abb0000 {
+		compatible = "qcom,pil-tz-generic";
+		reg = <0xabb0000 0x2000>;
+		status = "ok";
+		qcom,pas-id = <26>;
+		qcom,firmware-name = "evass";
+
+		memory-region = <&pil_cvp_mem>;
+	};
+
 	qcom,rmtfs_sharedmem@0 {
 		compatible = "qcom,sharedmem-uio";
 		reg = <0x0 0x280000>;
@@ -2620,6 +2638,7 @@
 #include "ipcc-test-shima.dtsi"
 #include "msm-arm-smmu-shima.dtsi"
 #include "shima-vidc.dtsi"
+#include "shima-cvp.dtsi"
 #include "shima-thermal.dtsi"
 #include "shima-gpu.dtsi"
 #include "shima-audio.dtsi"