Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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Merge "ARM: dts: msm: Add debug clock controller node for DIWALI"

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qctecmdr
2021-11-05 23:26:53 -07:00
committed by Gerrit - the friendly Code Review server
parent 1c8789b784 adc0ccc47f
commit ea2e12939b
2 changed files with 64 additions and 0 deletions
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8
qcom/diwali-rumi.dtsi
View File

@@ -200,3 +200,11 @@
<&sleep_clk>,
<&gcc GCC_DISP_AHB_CLK>;
};
&cpufreq_hw {
clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>;
};
&debugcc {
clocks = <&bi_tcxo>;
};

56
qcom/diwali.dtsi
View File

@@ -56,6 +56,7 @@
cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 4>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
@@ -80,6 +81,7 @@
cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 4>;
#cooling-cells = <2>;
};
@@ -94,6 +96,7 @@
cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 4>;
#cooling-cells = <2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
@@ -113,6 +116,7 @@
cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0 4>;
#cooling-cells = <2>;
};
@@ -127,6 +131,7 @@
cpu-idle-states = <&BIG_CPU_OFF &BIG_CPU_RAIL_OFF>;
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1 4>;
#cooling-cells = <2>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
@@ -146,6 +151,7 @@
cpu-idle-states = <&BIG_CPU_OFF &BIG_CPU_RAIL_OFF>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1 4>;
#cooling-cells = <2>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
@@ -165,6 +171,7 @@
cpu-idle-states = <&BIG_CPU_OFF &BIG_CPU_RAIL_OFF>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1 4>;
#cooling-cells = <2>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
@@ -184,6 +191,7 @@
cpu-idle-states = <&BIG_CPU_OFF &BIG_CPU_RAIL_OFF>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2 4>;
#cooling-cells = <2>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
@@ -1273,6 +1281,54 @@
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
};
cpufreq_hw: qcom,cpufreq-hw {
compatible = "qcom,cpufreq-hw-epss";
reg = <0x17d91000 0x1000>,
<0x17d92000 0x1000>,
<0x17d93000 0x1000>;
reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
qcom,lut-row-size = <4>;
qcom,skip-enable-check;
qcom,perf-lock-support;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int";
#freq-domain-cells = <2>;
};
qcom,cpufreq-hw-debug {
compatible = "qcom,cpufreq-hw-epss-debug";
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>,
<&cpufreq_hw 2>;
};
apsscc: syscon@17a80000 {
compatible = "syscon";
reg = <0x17a80000 0x21000>;
};
mccc: syscon@190ba000 {
compatible = "syscon";
reg = <0x190ba000 0x54>;
};
debugcc: debug-clock-controller@0 {
compatible = "qcom,diwali-debugcc";
qcom,gcc = <&gcc>;
qcom,videocc = <&videocc>;
qcom,dispcc = <&dispcc>;
qcom,camcc = <&camcc>;
qcom,gpucc = <&gpucc>;
qcom,apsscc = <&apsscc>;
qcom,mccc = <&mccc>;
clock-names = "xo_clk_src";
clocks = <&rpmhcc RPMH_CXO_CLK>;
#clock-cells = <1>;
};
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>;