Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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ARM: dts: msm: add phy aux & pll clk config1 register offset

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Add phy aux clk & pll clk config1 register offsets which needs to
be access for apps based L1ss sleep.

Change-Id: I2b3b0f4410a0caac4fadef839f1e5e1713b5503a
This commit is contained in:
Krishna Chaitanya Chundru
2023-11-06 12:06:55 +05:30
committed by Krishna chaitanya chundru
parent 9fe0e1b325
commit ed45d613ec
2 changed files with 13 additions and 0 deletions
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11
bindings/pci/pci-msm.txt
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@@ -423,6 +423,17 @@ interconnects:
value type: <u32>
Definition: Offset from PCIe PHY base to dump pcie phy status registers
- qcom,phy-aux-clk-config1-offset:
Usage: required
Value type: <u32>
Definition: Offset from PCIe PHY aux clk config register to disable FLL
- qcom,phy-pll-clk-enable1-offset:
Usage: required
Value type: <u32>
Definition: ffset from PCIe PHY base to enable ext clk buf mux to
eliminate VDDA leakage
==============
Root port node
==============

2
qcom/anorak-pcie.dtsi
View File

@@ -665,6 +665,8 @@
qcom,l1-2-th-value = <150>;
qcom,pcie-phy-ver = <114>;
qcom,phy-aux-clk-config1-offset = <0x1450>;
qcom,phy-pll-clk-enable1-offset = <0x1048>;
qcom,phy-status-offset = <0x1214>;
qcom,phy-status-bit = <7>;
qcom,phy-power-down-offset = <0x1240>;