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ARM: dts: msm: Update the PCIE clocks support on NEO platforms

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PCIE clocks and GDSC's are not required to be controlled from HLOS
on all NEO platforms. Hence add support for PCIE clocks and GDSC's
only on specific platforms that require them.

Change-Id: I94ddcd6bc3954d4da0dbcaa9ce566399deb4c9d7
This commit is contained in:
Kalpak Kawadkar
2022-08-29 16:23:11 +05:30
parent 51b501a79e
commit ee05bcde63
4 changed files with 110 additions and 53 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
qcom/neo-idp-mos.dtsi
View File

@@ -1,5 +1,46 @@
#include "neo-idp.dtsi"
#include <dt-bindings/clock/qcom,gcc-neo.h>
#include <dt-bindings/clock/qcom,tcsrcc.h>
&soc {
};
&tcsrcc {
protected-clocks = <TCSR_PCIE_0_CLKREF_EN>,
<TCSR_PCIE_1_CLKREF_EN>;
};
&gcc {
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo", "sleep_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
protected-clocks = <GCC_DDRSS_PCIE_SF_CLK>,
<GCC_PCIE_0_AUX_CLK>, <GCC_PCIE_0_AUX_CLK_SRC>,
<GCC_PCIE_0_CFG_AHB_CLK>, <GCC_PCIE_0_MSTR_AXI_CLK>,
<GCC_PCIE_0_PHY_RCHNG_CLK>, <GCC_PCIE_0_PHY_RCHNG_CLK_SRC>,
<GCC_PCIE_0_PIPE_CLK>, <GCC_PCIE_0_PIPE_CLK_SRC>,
<GCC_PCIE_0_SLV_AXI_CLK>, <GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<GCC_PCIE_1_AUX_CLK>, <GCC_PCIE_1_AUX_CLK_SRC>,
<GCC_PCIE_1_CFG_AHB_CLK>, <GCC_PCIE_1_MSTR_AXI_CLK>,
<GCC_PCIE_1_PHY_RCHNG_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>,
<GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>,
<GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<GCC_QMIP_PCIE_AHB_CLK>;
};
&gcc_pcie_0_gdsc {
status = "disabled";
};
&gcc_pcie_0_phy_gdsc {
status = "disabled";
};
&gcc_pcie_1_gdsc {
status = "disabled";
};
&gcc_pcie_1_phy_gdsc {
status = "disabled";
};

42
qcom/neo-qxr-mos.dtsi
View File

@@ -1,4 +1,46 @@
#include "neo-qxr.dtsi"
#include <dt-bindings/clock/qcom,gcc-neo.h>
#include <dt-bindings/clock/qcom,tcsrcc.h>
&soc {
};
&tcsrcc {
protected-clocks = <TCSR_PCIE_0_CLKREF_EN>,
<TCSR_PCIE_1_CLKREF_EN>;
};
&gcc {
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo", "sleep_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
protected-clocks = <GCC_DDRSS_PCIE_SF_CLK>,
<GCC_PCIE_0_AUX_CLK>, <GCC_PCIE_0_AUX_CLK_SRC>,
<GCC_PCIE_0_CFG_AHB_CLK>, <GCC_PCIE_0_MSTR_AXI_CLK>,
<GCC_PCIE_0_PHY_RCHNG_CLK>, <GCC_PCIE_0_PHY_RCHNG_CLK_SRC>,
<GCC_PCIE_0_PIPE_CLK>, <GCC_PCIE_0_PIPE_CLK_SRC>,
<GCC_PCIE_0_SLV_AXI_CLK>, <GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<GCC_PCIE_1_AUX_CLK>, <GCC_PCIE_1_AUX_CLK_SRC>,
<GCC_PCIE_1_CFG_AHB_CLK>, <GCC_PCIE_1_MSTR_AXI_CLK>,
<GCC_PCIE_1_PHY_RCHNG_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>,
<GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>,
<GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<GCC_QMIP_PCIE_AHB_CLK>;
};
&gcc_pcie_0_gdsc {
status = "disabled";
};
&gcc_pcie_0_phy_gdsc {
status = "disabled";
};
&gcc_pcie_1_gdsc {
status = "disabled";
};
&gcc_pcie_1_phy_gdsc {
status = "disabled";
};

41
qcom/neo.dtsi
View File

@@ -728,21 +728,11 @@
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
<&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo", "sleep_clk",
"pcie_0_pipe_clk", "pcie_1_pipe_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
protected-clocks = <GCC_DDRSS_PCIE_SF_CLK>,
<GCC_PCIE_0_AUX_CLK>, <GCC_PCIE_0_AUX_CLK_SRC>,
<GCC_PCIE_0_CFG_AHB_CLK>, <GCC_PCIE_0_MSTR_AXI_CLK>,
<GCC_PCIE_0_PHY_RCHNG_CLK>, <GCC_PCIE_0_PHY_RCHNG_CLK_SRC>,
<GCC_PCIE_0_PIPE_CLK>, <GCC_PCIE_0_PIPE_CLK_SRC>,
<GCC_PCIE_0_SLV_AXI_CLK>, <GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<GCC_PCIE_1_AUX_CLK>, <GCC_PCIE_1_AUX_CLK_SRC>,
<GCC_PCIE_1_CFG_AHB_CLK>, <GCC_PCIE_1_MSTR_AXI_CLK>,
<GCC_PCIE_1_PHY_RCHNG_CLK>, <GCC_PCIE_1_PHY_RCHNG_CLK_SRC>,
<GCC_PCIE_1_PIPE_CLK>, <GCC_PCIE_1_PIPE_CLK_SRC>,
<GCC_PCIE_1_SLV_AXI_CLK>, <GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<GCC_QMIP_PCIE_AHB_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -831,8 +821,6 @@
compatible = "qcom,tcsrcc", "syscon";
reg = <0x1fc0000 0x30000>;
reg-name = "cc_base";
protected-clocks = <TCSR_PCIE_0_CLKREF_EN>,
<TCSR_PCIE_1_CLKREF_EN>;
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -2399,6 +2387,31 @@
status = "ok";
};
&gcc_pcie_0_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
/delete-property/ qcom,support-hw-trigger;
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 0>;
};
&gcc_pcie_0_phy_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 3>;
};
&gcc_pcie_1_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 1>;
};
&gcc_pcie_1_phy_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 4>;
};
&cam_cc_bps_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";

39
qcom/neo_la.dtsi
View File

@@ -70,45 +70,6 @@
};
};
&tcsrcc {
/delete-property/ protected-clocks;
};
&gcc {
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
<&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo", "sleep_clk",
"pcie_0_pipe_clk", "pcie_1_pipe_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
/delete-property/ protected-clocks;
};
&gcc_pcie_0_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
/delete-property/ qcom,support-hw-trigger;
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 0>;
};
&gcc_pcie_0_phy_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 3>;
};
&gcc_pcie_1_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 1>;
};
&gcc_pcie_1_phy_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 4>;
};
&wpss_pas {
status = "disabled";
/delete-property/ memory-region;