mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-01-27 14:44:08 +00:00
ARM: dts: msm: Add PCIe nodes for ravelin
Add required PCIe device nodes for ravelin for HSP attach. Change-Id: Ief7c0e50b1fed9da6b8f37ea13f762424736b26d
This commit is contained in:
Vijayavardhan Vennapusa
@@ -1,3 +1,10 @@
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&soc {
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};
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&pcie0 {
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status = "ok";
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};
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&pcie0_msi {
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status = "ok";
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};
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270
qcom/ravelin-pcie.dtsi
Normal file
270
qcom/ravelin-pcie.dtsi
Normal file
@@ -0,0 +1,270 @@
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#include <dt-bindings/clock/qcom,gcc-ravelin.h>
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&soc {
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pcie0: qcom,pcie@1c00000 {
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compatible = "qcom,pci-msm";
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reg = <0x01c00000 0x3000>,
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<0x01c06000 0x2000>,
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<0x60000000 0xf1d>,
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<0x60000f20 0xa8>,
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<0x60001000 0x1000>,
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<0x60100000 0x100000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
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<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie0_msi>;
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perst-gpio = <&tlmm 32 0>;
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wake-gpio = <&tlmm 31 0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_perst_default
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&pcie0_clkreq_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_perst_default
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&pcie0_clkreq_sleep
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&pcie0_wake_default>;
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gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;
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vreg-1p8-supply = <&L16B>;
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vreg-0p9-supply = <&L5B>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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vreg-mx-supply = <&VDD_MX_LEVEL>;
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qcom,vreg-1p8-voltage-level = <1200000 1200000 15070>;
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qcom,vreg-0p9-voltage-level = <880000 880000 46890>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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19200000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_NOM
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RPMH_REGULATOR_LEVEL_NOM
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100000000>;
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interconnect-names = "icc_path";
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interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
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<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
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<&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
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<&pcie_0_pipe_clk>;
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clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
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"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
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"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
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"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
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"pcie_phy_refgen_clk",
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"pcie_ddrss_sf_tbu_clk",
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"pcie_aggre_noc_0_axi_clk",
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"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
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"pcie_pipe_clk_ext_src";
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max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <0>, <0>, <100000000>,
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<0>, <0>, <0>, <0>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "pcie_0_core_reset",
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"pcie_0_phy_reset";
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dma-coherent;
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qcom,smmu-sid-base = <0x1400>;
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iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
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<0x100 &apps_smmu 0x1401 0x1>;
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qcom,boot-option = <0x1>;
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qcom,aux-clk-freq = <20>; /* 19.2 MHz */
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qcom,drv-supported;
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qcom,no-l0s-supported;
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qcom,drv-l1ss-timeout-us = <5000>;
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qcom,l1-2-th-scale = <2>;
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qcom,l1-2-th-value = <150>;
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qcom,slv-addr-space-size = <0x4000000>;
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qcom,ep-latency = <10>;
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qcom,num-parf-testbus-sel = <0xb9>;
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qcom,config-recovery;
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qcom,pcie-phy-ver = <105>;
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qcom,phy-status-offset = <0x214>;
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qcom,phy-status-bit = <6>;
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qcom,phy-power-down-offset = <0x240>;
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qcom,phy-sequence = <0x0240 0x03 0x0
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0x0094 0x08 0x0
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0x0154 0x34 0x0
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0x016c 0x08 0x0
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0x0058 0x0f 0x0
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0x00a4 0x42 0x0
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0x0110 0x24 0x0
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0x011c 0x03 0x0
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0x0118 0xb4 0x0
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0x010c 0x02 0x0
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0x01bc 0x11 0x0
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0x00bc 0x82 0x0
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0x00d4 0x03 0x0
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0x00d0 0x55 0x0
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0x00cc 0x55 0x0
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0x00b0 0x1a 0x0
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0x00ac 0x0a 0x0
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0x00c4 0x68 0x0
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0x00e0 0x02 0x0
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0x00dc 0xaa 0x0
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0x00d8 0xab 0x0
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0x00b8 0x34 0x0
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0x00b4 0x14 0x0
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0x0158 0x01 0x0
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0x0074 0x06 0x0
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0x007c 0x16 0x0
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0x0084 0x36 0x0
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0x0078 0x06 0x0
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0x0080 0x16 0x0
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0x0088 0x36 0x0
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0x01b0 0x1e 0x0
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0x01ac 0xca 0x0
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0x01b8 0x18 0x0
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0x01b4 0xa2 0x0
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0x0050 0x07 0x0
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0x0010 0x01 0x0
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0x001c 0x31 0x0
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0x0020 0x01 0x0
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0x0024 0xde 0x0
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0x0028 0x07 0x0
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0x0030 0x4c 0x0
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0x0034 0x06 0x0
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0x0ee4 0x20 0x0
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0x0e84 0x75 0x0
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0x0e90 0x3f 0x0
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0x115c 0x7f 0x0
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0x1160 0xff 0x0
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0x1164 0xbf 0x0
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0x1168 0x3f 0x0
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0x116c 0xd8 0x0
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0x1170 0xdc 0x0
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0x1174 0xdc 0x0
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0x1178 0x5c 0x0
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0x117c 0x34 0x0
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0x1180 0xa6 0x0
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0x1190 0x34 0x0
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0x1194 0x38 0x0
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0x10d8 0x0f 0x0
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0x0e3c 0x12 0x0
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0x0e40 0x01 0x0
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0x10dc 0x00 0x0
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0x104c 0x08 0x0
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0x1050 0x08 0x0
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0x1044 0xf0 0x0
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0x11a4 0x38 0x0
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0x10cc 0xf0 0x0
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0x10f4 0x07 0x0
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0x1008 0x09 0x0
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0x1014 0x05 0x0
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0x0694 0x00 0x0
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0x0654 0x00 0x0
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0x06a8 0x0f 0x0
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0x0048 0x90 0x0
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0x0620 0xc1 0x0
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0x0388 0x77 0x0
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0x0398 0x0b 0x0
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0x02dc 0x05 0x0
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0x0200 0x00 0x0
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0x0244 0x03 0x0>;
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qcom,parf-debug-reg = <0x01B0 0x0024 0x0028 0x0224 0x0500
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0x04D0 0x04D4 0x03C0 0x0630 0x0230
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0x0000>;
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qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x0204 0x0730
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0x0734 0x0738 0x073C>;
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qcom,phy-debug-reg = <0x0068 0x0140 0x0144 0x0148 0x014C
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0x0150 0x0160 0x0178 0x0ED0 0x0EDC
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0x0F34 0x0F38 0x0f3C 0x0F40 0x0F44
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0x0F48 0x0F4C 0x0F50 0x0F54 0x0F58
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0x11E8 0x0A00 0x0A04 0x0A08 0x0A0C
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0x0A10 0x0A14 0x0A18 0x0C20 0x0214
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0x0218 0x021C 0x0220 0x0224 0x0228
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0x022C 0x0230 0x0234 0x0238 0x023C
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0x0600 0x0604 0x1204 0x1210>;
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status = "disabled";
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@0x17210040 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0x17210040 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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};
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@@ -1371,5 +1371,59 @@
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};
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};
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};
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pcie0 {
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pcie0_perst_default: pcie0_perst_default {
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mux {
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pins = "gpio32";
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function = "gpio";
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};
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config {
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pins = "gpio32";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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pcie0_clkreq_default: pcie0_clkreq_default {
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mux {
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pins = "gpio107";
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function = "pcie0_clkreq";
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};
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config {
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pins = "gpio107";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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pcie0_wake_default: pcie0_wake_default {
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mux {
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pins = "gpio31";
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function = "gpio";
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};
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config {
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pins = "gpio31";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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pcie0_clkreq_sleep: pcie0_clkreq_sleep {
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mux {
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pins = "gpio107";
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function = "gpio";
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};
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config {
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pins = "gpio107";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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};
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};
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@@ -213,3 +213,26 @@
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&tsens1 {
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status = "disabled";
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};
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&pcie0 {
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reg = <0x01c00000 0x3000>,
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<0x01c06000 0x2000>,
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<0x60000000 0xf1d>,
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<0x60000f20 0xa8>,
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<0x60001000 0x1000>,
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<0x60100000 0x100000>,
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<0x01c05000 0x1000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
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"rumi";
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qcom,target-link-speed = <0x1>;
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qcom,link-check-max-count = <200>; /* 1 sec */
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qcom,no-l1-supported;
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qcom,no-l1ss-supported;
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qcom,no-aux-clk-sync;
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status = "ok";
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};
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&pcie0_msi {
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status = "ok";
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};
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@@ -23,7 +23,7 @@
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chosen: chosen {
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stdout-path = "/soc/qcom,qup_uart@a88000:115200n8";
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bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat msm_rtb.filter=0x237 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on";
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bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat msm_rtb.filter=0x237 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none kpti=0 swiotlb=noforce cgroup.memory=nokmem,nosocket kswapd_per_node=2 slub_debug=- allow_file_spec_access cpufreq.default_governor=performance transparent_hugepage=never can.stats_timer=0 disable_dma32=on android12_only.will_be_removed_soon.memblock_nomap_remove=on pcie_ports=compat";
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};
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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@@ -2548,6 +2548,7 @@
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#include "ipcc-test-ravelin.dtsi"
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#include "ravelin-qupv3.dtsi"
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#include "ravelin-regulators.dtsi"
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#include "ravelin-pcie.dtsi"
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&qupv3_se7_2uart {
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status = "ok";
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