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https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
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Merge "dt-bindings: usb: Add bindings for MSM SSUSB"
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148
bindings/usb/msm-ssusb.txt
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148
bindings/usb/msm-ssusb.txt
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MSM SuperSpeed USB3.0 SoC controller
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Required properties :
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- compatible : should be "qcom,dwc-usb3-msm"
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- reg: Address and length of the register set for the device
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Required regs are:
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"core_base" : usb controller register set
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- interrupts: IRQ lines used by this controller
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- interrupt-names : Interrupt resource entries are :
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"pwr_event_irq" : Interrupt to controller for asynchronous events in LPM.
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Used for SS-USB power events.
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- clocks: a list of phandles to the controller clocks. Use as per
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
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property. Required clocks are "xo", "iface_clk", "core_clk", "sleep_clk"
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and "utmi_clk".
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- resets: reset specifier pair consists of phandle for the reset provider
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and reset lines used by this controller.
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- reset-names: reset signal name strings sorted in the same order as the resets
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property.
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Optional properties :
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- reg: Additional registers
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"ahb2phy_base" : top-level register to configure read/write wait cycle with
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both QMP and QUSB PHY registers.
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- Refer to "Documentation/devicetree/bindings/arm/msm/msm_bus.txt" for
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below optional properties:
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- qcom,msm_bus,name
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- qcom,msm_bus,num_cases
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- qcom,msm_bus,num_paths
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- qcom,msm_bus,vectors
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- qcom,default-bus-vote: To use default bus voting other than NOMINAL. Default is NOMINAL.
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- interrupt-names : Optional interrupt resource entries are:
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"ss_phy_irq" : Interrupt from super speed phy for wake up notification.
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"hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM.
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"dp_hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM
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going through PDC. (use qcom,use-pdc-interrupts property)
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"dm_hs_phy_irq" : Interrupt from HS PHY for asynchronous events in LPM
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going through PDC. (use qcom,use-pdc-interrupts property)
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- clocks: a list of phandles to the controller clocks. Use as per
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
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property. Optional clocks are "bus_aggr_clk", "noc_aggr_clk" and "cfg_ahb_clk".
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- qcom,charging-disabled: If present then battery charging using USB
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is disabled.
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- vbus_dwc3-supply: phandle to the 5V VBUS supply regulator used for host mode.
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- USB3_GDSC-supply : phandle to the globally distributed switch controller
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regulator node to the USB controller.
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- dpdm-supply: phandle to dpdm supply which will be used to drive dp/dm lines
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in high-z state.
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- qcom,dwc-usb3-msm-tx-fifo-size: If present, represents RAM size available for
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TX fifo allocation in bytes
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- qcom,lpm-to-suspend-delay-ms: Indicates timeout (in milliseconds) to release wakeup source
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after USB is kept into LPM.
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- qcom,disable-dev-mode-pm: If present, it disables PM runtime functionality for device mode.
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- qcom,core-clk-rate: If present, indicates clock frequency to be set for USB master clock.
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- qcom,core-clk-rate-hs: If present, indicates min core clock frequency required to support
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hs speed.
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- qcom,use-pdc-interrupts: It present, it configures provided PDC IRQ with required
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configuration for wakeup functionality.
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- extcon: phandles to external connector devices. First phandle should point to
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external connector, which provide type-C based "USB" cable events, the
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second should point to external connector device, which provide type-C
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"USB-HOST" cable events. A single phandle may be specified if a single
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connector device provides both "USB" and "USB-HOST" events. An optional
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third phandle may be specified for EUD based attach/detach events. A
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mandatory fourth phandle has to be specified to provide microUSB based
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"USB" cable events. An optional fifth phandle may be specified to provide
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microUSB based "USB-HOST" cable events. Only the fourth phandle may be
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specified if a single connector device provides both "USB" and "USB-HOST"
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events.
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- qcom,num-gsi-evt-buffs: If present, specifies number of GSI based hardware accelerated
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event buffers. 1 event buffer is needed per h/w accelerated endpoint.
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- qcom,gsi-reg-offset: USB GSI wrapper registers offset. It is must to provide this
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if qcom,num-gsi-evt-buffs property is specified. Check dwc3-msm driver for order
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and name of register offset need to provide.
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- qcom,gsi-disable-io-coherency: IO-coherency is enabled by default in usb gsi driver.
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This property disables io-coherency in usb gsi driver.
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- qcom,pm-qos-latency: This represents max tolerable CPU latency in microsecs,
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which is used as a vote by driver to get max performance in perf mode.
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- qcom,smmu-s1-bypass: If present, configure SMMU to bypass stage 1 translation.
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- qcom,dbm-version: If present, specifies DBM version. Currently "1.4" or "1.5"
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are supported. If omitted, assume HW supports "1.5".
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- qcom,reset-ep-after-lpm-resume: If present, dbm requires ep reset after
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going to lpm
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- qcom,host-poweroff-in-pm-suspend: If present, allow PM suspend to happen
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irrespective of runtimePM state of host and power collapse the core.
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This also leads to reset-resume of connected devices on PM resume.
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- qcom,default-mode-none: If present, do not start any mode on probe for an OTG
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capable DWC3 which does not have extcon handle.
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- qcom,default-mode-host: If present, start host mode on probe for an OTG
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capable DWC3 which does not have extcon handle.
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Sub nodes:
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- Sub node for "DWC3- USB3 controller".
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This sub node is required property for device node. The properties of this subnode
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are specified in dwc3.txt.
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Example MSM USB3.0 controller device node :
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usb@f9200000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0xf9200000 0xfc000>,
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<0xf9b3e000 0x3ff>;
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reg-names = "core_base",
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"ahb2phy_base",
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interrupts = <0 133 0>;
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interrupt-names = "hs_phy_irq";
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vbus_dwc3-supply = <&pm8941_mvs1>;
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USB3_GDSC-supply = <&gdsc_usb30>;
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qcom,dwc-usb3-msm-dbm-eps = <4>
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qcom,dwc_usb3-adc_tm = <&pm8941_adc_tm>;
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qcom,dwc-usb3-msm-tx-fifo-size = <29696>;
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qcom,usb-dbm = <&dbm_1p4>;
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qcom,lpm-to-suspend-delay-ms = <2>;
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qcom,num-gsi-evt-buffs = <0x2>;
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qcom,pm-qos-latency = <2>;
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qcom,msm_bus,name = "usb3";
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qcom,msm_bus,num_cases = <2>;
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qcom,msm_bus,num_paths = <1>;
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qcom,msm_bus,vectors =
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<61 512 0 0>,
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<61 512 240000000 960000000>;
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clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
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<&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>,
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<&clock_gcc clk_gcc_aggre1_usb3_axi_clk>,
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<&clock_rpmcc RPM_AGGR2_NOC_CLK>,
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<&clock_gcc clk_gcc_usb30_mock_utmi_clk>,
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<&clock_gcc clk_gcc_usb30_sleep_clk>,
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<&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
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<&clock_gcc clk_cxo_dwc3_clk>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "noc_aggr_clk",
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"utmi_clk", "sleep_clk", "cfg_ahb_clk", "xo";
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resets = <&clock_gcc GCC_USB_30_BCR>;
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reset-names = "core_reset";
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dwc3@f9200000 {
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compatible = "synopsys,dwc3";
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reg = <0xf9200000 0xfc000>;
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interrupts = <0 131 0>, <0 179 0>;
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interrupt-names = "irq", "otg_irq";
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tx-fifo-resize;
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};
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};
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