This snapshot is taken from msm-4.19 as of commit ed241f132720397
("dt-bindings: Add devicetree bindings to devicetree project") and
updated as needed.
Change-Id: I2fed806703bc459059aa7038a16cc212a31ac673
Add the CX GDSC to the IOMMU node so that we can make sure that it is
enabled before trying to access IOMMU registers.
Change-Id: Ic0dedbad2410d2131dec75d54159f0fba0e3aa6d
Move the definition of the IOMMU clocks to the GPU device so that they
are identified with an actual platform device instead of a pseudo device.
Change-Id: Ic0dedbadaa12e748db585cf164ed5e4ea45c43c0
Add "qcom,thermal-mitigation" property to configure fast charging
current for different system thermal mitigation levels.
Change-Id: Ia07b24d85d904e6e623ba547973f5a5779305784
Dummy clock nodes are required for clocks client to request, so add support
for the same. Also add the dummy GDSCs required by clients.
Change-Id: I5455dcc6825138c88d682235fcf6224ffdf5aa06
Enable haptics device node and update parameters according to the
LRA actuator installed on Lahaina QRD device.
Change-Id: Ica7b30122c0374a88d667052c48e5b124b7274e4
Set CNSS DTSI node for S12B voltage regulator to 1.35V. It was
initially set to 1.256V since AOP voltage range settings for this
regulator was not correct.
Change-Id: Ic2409e46b0c5e9c46703fcbb17deddc1ac045d9f
CVP hardware programming guide requires inserting a AXI clock reset
pulse in CVP power on sequence.
Change-Id: I10dd30b229a6a772a247144986da52c917268e38
Shima uses PM8350, PM8350C and PMR735B. Add stub regulator
support for the same to allow the clients to vote on them.
Change-Id: Iee9d9f259b267156537b442efeb4eea29bae4717
on Lahaina QRD device, there's no SWR DMIC connected. Set
qcom,swr-dmic-max-devs to 0 and disable SWR DMIC on QRD device.
Change-Id: Ice7418b4e555da9a16f3444e09b80a45de915236
Mark the APPS SMMU interconnect votes as active-only for the
Lahaina target. This allows for interconnect votes to be
maintained when the CPU subsystem is active, which is all that
is required.
Change-Id: I27824d0d6ec1754df6519698cf77f13df58a0ea1
Add documentation for the ARM SMMU qcom,active-only property.
This property denotes what set of CPUSS contexts (active/dual)
an interconnect vote needs to be maintained in.
Change-Id: I3fc89c5ce39275150288cf8bcdc258d061058f8a
Update below DT entries based on testing on the target.
- Move memory node outside of vm-config node and provide
static S2 mappings until VMM is ready.
- Update chosen node to support initramfs functionality.
- Remove interrupt controller reference from arch_timer.
Change-Id: Id59aa9e21cdc356e3664ebb4323c3ecefb9f1f3c
Add pinctrl node with compatiability of qcom,shima-pinctrl,
to enable Top Level Mode Multiplexer block(TLMM) on Shima SoC.
Change-Id: Iee97d663855df2578e751c82b6088e2db39db927
