Add the QMP and QMP DEBUGFS node to facilitiate communication with AOP.
The QMP driver sends messages using the AOP msgram with a mailbox like
protocol.
Change-Id: Id67ef57b2895f98a486d5ee2724205f1d6b5e41e
The ION carveout heap manages the carveouts under its domain
by relying on the assumption that the kernel is aware of this
memory. When the memory is marked as "no-map", the kernel
does not maintain any information about the memory, which
prevents the carveout heap from managing the memory. Thus,
allow for the carveout heap memory to be mapped by the kernel.
Change-Id: I6516d2cd8fcacdb975a3190254e79bbce51e1d24
Add lahaina-usb.dtsi which defines USB controller nodes and no-op
PHY. In addition, add entries for the emulation PHY to
lahaina-rumi.dtsi with overrides to limit the USB instances to
high-speed, peripheral-only.
Change-Id: I987a18c07c5406de3c924fcf03db13a72e9ab2de
To prevent the possibility of running out of stream-matching
entries (SMEs) on the KGSL SMMU in cases where all the SMEs
are required, disable the coherent KGSL IOMMU test device.
Change-Id: I1d1cf1a4530680de91c839d22f057b807765111d
Update the board-id property to include major and minor ids as well
for the bootloader to pick the correct version of devicetree.
Change-Id: I9403d2b2fb88e55db4e68ceea9d884d507167cc7
The PIL drivers need to vote for bandwidth across DDR and
crypto subsytem, such that the secure world can perform
initialization and authorization of the firmware blobs.
Hence add a device-tree node indicating the corresponding
interconnect.
Change-Id: If5626ad20638434e39a7d4aa0f02149a72bdaf12
Add edac node with compatibility of arm,arm64-kryo-cpu-erp,
to enable error reporting capability for L1/L2 & L3 memories
on Lahaina SoC.
Change-Id: Id561334e40c0aaf04348db90df4a30252ded2432
Fix the size of the register space for the graphics SMMU,
and enable it, as well as the associated test devices.
Change-Id: I5963b9d5a5fb0ad1d55a1e2011ee1bfb5d961fee
Make the LLCC device-tree node compatible with "qcom,lahaina-llcc"
so that it could be matched with the LLCC driver for Lahaiana
platform.
Change-Id: If362950496a2e9b6f073c59ed703072da741a67d
Add the initial set of devices that describe the APPS
and graphics SMMU register spaces for the Lahaina.
Change-Id: I308c55d050cd199f5a9d97fdf77319f4b77c8c30
Add the secure buffer device for Lahaina to secure memory
buffers, and protect them against unauthorized access.
Change-Id: I7b07d32bb51667e18666295a2504dd029cb22c3f
Add stub interconnect devices for aggre1_noc, aggre2_noc,
config_noc, dc_noc, gem_noc, lpass_ag_noc, mc_virt_noc,
mmss_noc, nsp_noc, system_noc, This will allow consumers to
get their path and set bandwidth constraints on them.
Change-Id: Ic2ec48af802b6d763c857482facddf4367570b24
Add the Secure Channel Manager device-tree node to
communicate with the secure world on Lahaina platform.
Change-Id: I7002f90265830131acc2fca1f93934932d56eff4
Add pinctrl node with compatiability of qcom,lahaina-pinctrl,
to enable Top Level Mode Multiplexer block(TLMM) on Lahaina SoC.
Change-Id: Iac61248547061d5cb2ec42e442117f676f54ff77
Add stub clock devices for rpmh, aop, gcc, videocc, camcc, dispcc
and gpucc clock controllers on the Lahaina SoC. This allows consumers
to reference dummy clocks until full functionality is in place.
Change-Id: Idd7c45aaa301cd0688c4f7ca59ddfe3447bf996e
Add stub regulator devices for the SMPS, LDO, and BOB regulators
found on the PM8350, PM8350C, and PM8008 PMIC chips which are
used on Lahaina boards. This ensures that consumers can make use
of the regulators which have appropriate voltage limits.
Change-Id: I87bd3dbd9b9dc5d082fe90689edcd6fa090e7739
