Add documentation about pdc interrupt controller node
and dt-bindings. This is taken from msm-4.14 commit
("aaa3cbba7c").
Change-Id: Id31d0b85cd2ccbe535e94595db7e60d3466d1fdc
Newer SoC's do not need the SPI register to be written from secure
firmware. Remove the DT property.
Change-Id: If02010f92f5830013966c5344dce93911e055b1b
Some interrupt controllers in a SoC, are always powered on and have a
select interrupts routed to them, so that they can wakeup the SoC from
suspend. Add wakeup-parent DT property to refer to these interrupt
controllers.
Change-Id: I3601e3a037250a77253dce281c5f503400a6dc26
In addition to configuring the PDC, additional registers that interface
the GIC have to be configured to match the GPIO type. The registers on
some QCOM SoCs are access restricted, while on other SoCs are not. They
SoCs with access restriction to these SPI registers need to be written
from the firmware using the SCM interface. Add a flag to indicate if the
register is to be written using SCM interface.
Change-Id: I89ba52ded2451071973b81c83a53964d7ec2e486
Add snapshot of the device-tree bindings' YAML files that has
GPL-2.0 or BSD-2-Clause license. The snapshot is taken from
Android Common Kernel's android-mainline branch as of commit-id
<b41e0f1228c15d6> (ANDROID: update abi_gki_aarch64.xml for 5.2-rc5).
Change-Id: I03c75ed9aeec161dac792e18f5ab991a94de6dce
