Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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dt-bindings: pdc: Add SPI config register

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In addition to configuring the PDC, additional registers that interface
the GIC have to be configured to match the GPIO type. The registers on
some QCOM SoCs are access restricted, while on other SoCs are not. They
SoCs with access restriction to these SPI registers need to be written
from the firmware using the SCM interface. Add a flag to indicate if the
register is to be written using SCM interface.

Change-Id: I89ba52ded2451071973b81c83a53964d7ec2e486
This commit is contained in:
Lina Iyer
2019-02-13 12:00:11 -07:00
committed by Maulik Shah
parent d9bae78ade
commit 65b8a22ac0
1 changed files with 10 additions and 2 deletions
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12
bindings/interrupt-controller/qcom,pdc.txt
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@@ -23,7 +23,8 @@ Properties:
- reg:
Usage: required
Value type: <prop-encoded-array>
Definition: Specifies the base physical address for PDC hardware.
Definition: Specifies the base physical address for PDC hardware and
the interrupt type configuration register.
- interrupt-cells:
Usage: required
@@ -50,15 +51,22 @@ Properties:
The second element is the GIC hwirq number for the PDC port.
The third element is the number of interrupts in sequence.
- qcom,scm-spi-cfg:
Usage: optional
Value type: <bool>
Definition: Specifies if the SPI configuration registers have to be
written from the firmware.
Example:
pdc: interrupt-controller@b220000 {
compatible = "qcom,sdm845-pdc";
reg = <0xb220000 0x30000>;
reg = <0xb220000 0x30000>, <0x179900f0 0x60>;
qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
qcom,scm-spi-cfg;
};
DT binding of a device that wants to use the GIC SPI 514 as a wakeup