Evolution-x-devices/kernel_xiaomi_sm8450-devicetrees
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kernel_xiaomi_sm8450-device…/qcom/holi-usb.dtsi
Pavankumar Kondeti c1f9e55bc3 ARM: dts: msm: Remove qcom,dwc-usb3-msm-tx-fifo-size property 
MSM USB DWC3 driver does not depend on this property to know
the TXFIFO size in the USB controller. Remove any reference to
qcom,dwc-usb3-msm-tx-fifo-size property.

Change-Id: I321f041b44cb35033f9bcdd1b6cba0f3fb9da8b5
2022-01-21 06:29:43 +05:30

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#include <dt-bindings/clock/qcom,gcc-holi.h>
#include <dt-bindings/phy/qcom,holi-qmp-usb3.h>
&soc {
/* Primary USB port related controller */
usb0: ssusb@4e00000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0x4e00000 0x100000>;
reg-names = "core_base";
iommus = <&apps_smmu 0xe0 0x0>;
qcom,iommu-dma = "atomic";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
dma-ranges;
interrupts-extended = <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<&wakegic 12 IRQ_TYPE_LEVEL_HIGH>,
<&wakegic 93 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq";
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"xo", "sleep_clk", "utmi_clk";
resets = <&gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset";
USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
dpdm-supply = <&qusb_phy0>;
qcom,usb-charger;
qcom,core-clk-rate = <133333333>;
qcom,core-clk-rate-hs = <66666667>;
qcom,default-bus-vote = <2>; /* use svs bus voting */
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
interconnects = <&system_noc MASTER_USB3_0 &bimc SLAVE_EBI>,
<&system_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>;
qcom,num-gsi-evt-buffs = <0x3>;
qcom,gsi-reg-offset =
<0x0fc /* GSI_GENERAL_CFG */
0x110 /* GSI_DBL_ADDR_L */
0x120 /* GSI_DBL_ADDR_H */
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
dwc3@4e00000 {
compatible = "snps,dwc3";
reg = <0x4e00000 0xcd00>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&qusb_phy0>, <&usb_qmp_dp_phy>;
tx-fifo-resize;
linux,sysdev_is_parent;
snps,disable-clk-gating;
snps,is-utmi-l1-suspend;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis_u2_susphy_quirk;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
dr_mode = "otg";
};
};
/* Primary USB port related QUSB2 PHY */
qusb_phy0: qusb@162b000 {
compatible = "qcom,qusb2phy-v2";
reg = <0x0162b000 0x400>,
<0x1b40268 0x4>,
<0x0162f014 0x4>,
<0x0162a000 0x4>;
reg-names = "qusb_phy_base", "efuse_addr",
"refgen_north_bg_reg_addr",
"eud_enable_reg";
qcom,efuse-bit-pos = <25>;
qcom,efuse-num-bits = <3>;
vdd-supply = <&L18A>;
vdda18-supply = <&L2A>;
vdda33-supply = <&L3A>;
refgen-supply = <&L22A>;
qcom,vdd-voltage-level = <0 880000 880000>;
qcom,qusb-phy-reg-offset =
<0x240 /* QUSB2PHY_PORT_TUNE1 */
0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */
0x210 /* QUSB2PHY_PWR_CTRL1 */
0x230 /* QUSB2PHY_INTR_CTRL */
0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */
0x254 /* QUSB2PHY_TEST1 */
0x198 /* PLL_BIAS_CONTROL_2 */
0x27c /* QUSB2PHY_DEBUG_CTRL1 */
0x280 /* QUSB2PHY_DEBUG_CTRL2 */
0x284 /* QUSB2PHY_DEBUG_CTRL3 */
0x288 /* QUSB2PHY_DEBUG_CTRL4 */
0x2a0>; /* QUSB2PHY_STAT5 */
qcom,qusb-phy-init-seq =
/* <value reg_offset> */
<0x23 0x210 /* PWR_CTRL1 */
0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
0x7c 0x18c /* PLL_CLOCK_INVERTERS */
0x80 0x2c /* PLL_CMODE */
0x0a 0x184 /* PLL_LOCK_DELAY */
0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
0x40 0x194 /* PLL_BIAS_CONTROL_1 */
0x22 0x198 /* PLL_BIAS_CONTROL_2 */
0x21 0x214 /* PWR_CTRL2 */
0x08 0x220 /* IMP_CTRL1 */
0x58 0x224 /* IMP_CTRL2 */
0x45 0x240 /* TUNE1 */
0x29 0x244 /* TUNE2 */
0xca 0x248 /* TUNE3 */
0x04 0x24c /* TUNE4 */
0x03 0x250 /* TUNE5 */
0x30 0x23c /* CHG_CTRL2 */
0x22 0x210>; /* PWR_CTRL1 */
qcom,qusb-phy-host-init-seq =
/* <value reg_offset> */
<0x23 0x210 /* PWR_CTRL1 */
0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
0x7c 0x18c /* PLL_CLOCK_INVERTERS */
0x80 0x2c /* PLL_CMODE */
0x0a 0x184 /* PLL_LOCK_DELAY */
0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
0x40 0x194 /* PLL_BIAS_CONTROL_1 */
0x22 0x198 /* PLL_BIAS_CONTROL_2 */
0x21 0x214 /* PWR_CTRL2 */
0x08 0x220 /* IMP_CTRL1 */
0x58 0x224 /* IMP_CTRL2 */
0x45 0x240 /* TUNE1 */
0x29 0x244 /* TUNE2 */
0xca 0x248 /* TUNE3 */
0x04 0x24c /* TUNE4 */
0x03 0x250 /* TUNE5 */
0x30 0x23c /* CHG_CTRL2 */
0x22 0x210>; /* PWR_CTRL1 */
phy_type= "utmi";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "ref_clk_src";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
reset-names = "phy_reset";
};
/* Primary USB port related QMP USB DP Combo PHY */
usb_qmp_dp_phy: ssphy@1630000 {
compatible = "qcom,usb-ssphy-qmp-dp-combo";
reg = <0x1630000 0x3000>;
reg-names = "qmp_phy_base";
vdd-supply = <&L16A>;
qcom,vdd-voltage-level = <0 880000 880000>;
core-supply = <&L22A>;
qcom,qmp-phy-init-seq =
/* <reg_offset, value, delay> */
<USB3PHY_QSERDES_COM_PLL_IVCO 0x07 0
USB3PHY_QSERDES_COM_SYSCLK_EN_SEL 0x14 0
USB3PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x08 0
USB3PHY_QSERDES_COM_CLK_SELECT 0x30 0
USB3PHY_QSERDES_COM_SYS_CLK_CTRL 0x02 0
USB3PHY_QSERDES_COM_RESETSM_CNTRL2 0x08 0
USB3PHY_QSERDES_COM_CMN_CONFIG 0x16 0
USB3PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x01 0
USB3PHY_QSERDES_COM_HSCLK_SEL 0x80 0
USB3PHY_QSERDES_COM_DEC_START_MODE0 0x82 0
USB3PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0
USB3PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0
USB3PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
USB3PHY_QSERDES_COM_CP_CTRL_MODE0 0x06 0
USB3PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
USB3PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
USB3PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00 0
USB3PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x3f 0
USB3PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x01 0
USB3PHY_QSERDES_COM_VCO_TUNE1_MODE0 0xc9 0
USB3PHY_QSERDES_COM_CORECLK_DIV_MODE0 0x0a 0
USB3PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00 0
USB3PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
USB3PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x15 0
USB3PHY_QSERDES_COM_LOCK_CMP_EN 0x04 0
USB3PHY_QSERDES_COM_CORE_CLK_EN 0x00 0
USB3PHY_QSERDES_COM_LOCK_CMP_CFG 0x00 0
USB3PHY_QSERDES_COM_VCO_TUNE_MAP 0x00 0
USB3PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0
USB3PHY_QSERDES_COM_SSC_EN_CENTER 0x01 0
USB3PHY_QSERDES_COM_SSC_PER1 0x31 0
USB3PHY_QSERDES_COM_SSC_PER2 0x01 0
USB3PHY_QSERDES_COM_SSC_ADJ_PER1 0x00 0
USB3PHY_QSERDES_COM_SSC_ADJ_PER2 0x00 0
USB3PHY_QSERDES_COM_SSC_STEP_SIZE1 0x85 0
USB3PHY_QSERDES_COM_SSC_STEP_SIZE2 0x07 0
USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0b 0
USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4e 0
USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x18 0
USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
USB3PHY_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
USB3PHY_QSERDES_RXA_SIGDET_CNTRL 0x03 0
USB3PHY_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x16 0
USB3PHY_QSERDES_RXA_RX_MODE_00 0x05 0
USB3PHY_QSERDES_RXA_VGA_CAL_CNTRL2 0x03 0
USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0b 0
USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4e 0
USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18 0
USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
USB3PHY_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
USB3PHY_QSERDES_RXB_SIGDET_CNTRL 0x03 0
USB3PHY_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x16 0
USB3PHY_QSERDES_RXB_RX_MODE_00 0x05 0
USB3PHY_QSERDES_RXB_VGA_CAL_CNTRL2 0x03 0
USB3PHY_QSERDES_TXA_HIGHZ_DRVR_EN 0x10 0
USB3PHY_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
USB3PHY_QSERDES_TXA_LANE_MODE_1 0x16 0
USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x09 0
USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x06 0
USB3PHY_QSERDES_TXB_HIGHZ_DRVR_EN 0x10 0
USB3PHY_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
USB3PHY_QSERDES_TXB_LANE_MODE_1 0x16 0
USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x09 0
USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x06 0
USB3PHY_PCS_FLL_CNTRL2 0x83 0
USB3PHY_PCS_FLL_CNT_VAL_L 0x09 0
USB3PHY_PCS_FLL_CNT_VAL_H_TOL 0xa2 0
USB3PHY_PCS_FLL_MAN_CODE 0x40 0
USB3PHY_PCS_FLL_CNTRL1 0x02 0
USB3PHY_PCS_LOCK_DETECT_CONFIG1 0xd1 0
USB3PHY_PCS_LOCK_DETECT_CONFIG2 0x1f 0
USB3PHY_PCS_LOCK_DETECT_CONFIG3 0x47 0
USB3PHY_PCS_POWER_STATE_CONFIG2 0x1b 0
USB3PHY_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x75 0
USB3PHY_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x75 0
USB3PHY_PCS_RX_SIGDET_LVL 0xcc 0
USB3PHY_PCS_TXMGN_V0 0x9f 0
USB3PHY_PCS_TXMGN_V1 0x9f 0
USB3PHY_PCS_TXMGN_V2 0xb7 0
USB3PHY_PCS_TXMGN_V3 0x4e 0
USB3PHY_PCS_TXMGN_V4 0x65 0
USB3PHY_PCS_TXMGN_LS 0x6b 0
USB3PHY_PCS_TXDEEMPH_M6DB_V0 0x15 0
USB3PHY_PCS_TXDEEMPH_M3P5DB_V0 0x0d 0
USB3PHY_PCS_TXDEEMPH_M6DB_V1 0x15 0
USB3PHY_PCS_TXDEEMPH_M3P5DB_V1 0x0d 0
USB3PHY_PCS_TXDEEMPH_M6DB_V2 0x15 0
USB3PHY_PCS_TXDEEMPH_M3P5DB_V2 0x0d 0
USB3PHY_PCS_TXDEEMPH_M6DB_V3 0x15 0
USB3PHY_PCS_TXDEEMPH_M3P5DB_V3 0x1d 0
USB3PHY_PCS_TXDEEMPH_M6DB_V4 0x15 0
USB3PHY_PCS_TXDEEMPH_M3P5DB_V4 0x0d 0
USB3PHY_PCS_TXDEEMPH_M6DB_LS 0x15 0
USB3PHY_PCS_TXDEEMPH_M3P5DB_LS 0x0d 0
USB3PHY_PCS_REFGEN_REQ_CONFIG1 0x21 0
USB3PHY_PCS_REFGEN_REQ_CONFIG2 0x60 0
USB3PHY_PCS_RATE_SLEW_CNTRL 0x02 0
USB3PHY_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x04 0
USB3PHY_PCS_TSYNC_RSYNC_TIME 0x44 0
USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0
USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
USB3PHY_PCS_RCVR_DTCT_DLY_U3_L 0x40 0
USB3PHY_PCS_RCVR_DTCT_DLY_U3_H 0x00 0
USB3PHY_PCS_RXEQTRAINING_WAIT_TIME 0x75 0
USB3PHY_PCS_LFPS_TX_ECSTART_EQTLOCK 0x86 0
USB3PHY_PCS_RXEQTRAINING_RUN_TIME 0x13 0
USB3PHY_PCS_LFPS_DET_HIGH_COUNT_VAL 0x04 0
0xffffffff 0xffffffff 0>;
qcom,qmp-phy-reg-offset =
<USB3PHY_PCS_PCS_STATUS
USB3PHY_PCS_AUTONOMOUS_MODE_CTRL
USB3PHY_PCS_LFPS_RXTERM_IRQ_CLEAR
USB3PHY_PCS_POWER_DOWN_CONTROL
USB3PHY_PCS_SW_RESET
USB3PHY_PCS_START_CONTROL
USB3PHY_PCS_MISC_TYPEC_CTRL
USB3PHY_COM_POWER_DOWN_CTRL
USB3PHY_COM_SW_RESET
USB3PHY_COM_RESET_OVRD_CTRL
USB3PHY_COM_PHY_MODE_CTRL
USB3PHY_COM_TYPEC_CTRL
USB3PHY_PCS_MISC_CLAMP_ENABLE>;
clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
"ref_clk", "com_aux_clk";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
reset-names = "global_phy_reset", "phy_reset";
};
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
usb_audio_qmi_dev {
compatible = "qcom,usb-audio-qmi-dev";
iommus = <&apps_smmu 0x0af 0x0>;
qcom,iommu-dma = "disabled";
qcom,usb-audio-stream-id = <0xf>;
qcom,usb-audio-intr-num = <2>;
};
};
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