mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 08:51:30 +00:00
c1f9e55bc3
MSM USB DWC3 driver does not depend on this property to know the TXFIFO size in the USB controller. Remove any reference to qcom,dwc-usb3-msm-tx-fifo-size property. Change-Id: I321f041b44cb35033f9bcdd1b6cba0f3fb9da8b5
63 lines
1.6 KiB
Plaintext
63 lines
1.6 KiB
Plaintext
&soc {
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usb: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x0a600000 0x100000>;
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reg-names = "core_base";
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iommus = <&apps_smmu 0x1a0 0x0>;
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qcom,iommu-dma = "bypass";
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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dma-ranges;
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interrupts = <0 130 0>;
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interrupt-names = "pwr_event_irq";
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USB3_GDSC-supply = <&gcc_usb30_gdsc>;
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clocks = <&gcc GCC_USB30_MASTER_CLK>,
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<&gcc GCC_USB30_SLV_AHB_CLK>,
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<&gcc GCC_USB30_MSTR_AXI_CLK>,
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<&gcc GCC_USB30_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SLEEP_CLK>,
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<&gcc GCC_USB3_PRIM_CLKREF_EN>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk", "xo";
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resets = <&gcc GCC_USB30_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x208 /* GSI_DBL_ADDR_L */
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0x224 /* GSI_DBL_ADDR_H */
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0x240 /* GSI_RING_BASE_ADDR_L */
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0x25c /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0x0a600000 0xcd00>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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linux,sysdev_is_parent;
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snps,disable-clk-gating;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,ssp-u3-u0-quirk;
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snps,usb3-u1u2-disable;
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tx-fifo-resize;
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maximum-speed = "super-speed-plus";
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dr_mode = "otg";
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snps,xhci-imod-value = <4000>;
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};
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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};
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