mirror of
https://github.com/Evolution-X-Devices/kernel_xiaomi_sm8450-devicetrees
synced 2026-02-01 04:59:05 +00:00
9ac2a5d80b
Add reset control nodes for UFS PHY so that UFS PHY driver can control its SW reset through UFS host's address space. Change-Id: I8ef347733d611af7dfb1a9ecce10f8a5b5898e9b
1698 lines
40 KiB
Plaintext
1698 lines
40 KiB
Plaintext
#include <dt-bindings/clock/qcom,aop-qmp.h>
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#include <dt-bindings/clock/qcom,camcc-lahaina.h>
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#include <dt-bindings/clock/qcom,dispcc-lahaina.h>
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#include <dt-bindings/clock/qcom,gcc-lahaina.h>
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#include <dt-bindings/clock/qcom,gpucc-lahaina.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,videocc-lahaina.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interconnect/qcom,lahaina.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Qualcomm Technologies, Inc. Lahaina";
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compatible = "qcom,lahaina";
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qcom,msm-id = <415 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases {
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ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
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serial0 = &qupv3_se3_2uart;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cache-size = <0x8000>;
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cpu-idle-states = <&SLVR_RAIL_OFF>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x200000>;
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cache-size = <0x8000>;
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cpu-idle-states = <&SLVR_RAIL_OFF>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cache-size = <0x8000>;
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cpu-idle-states = <&SLVR_RAIL_OFF>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cache-size = <0x8000>;
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1024>;
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dynamic-power-coefficient = <100>;
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cpu-idle-states = <&SLVR_RAIL_OFF>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cache-size = <0x20000>;
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1946>;
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dynamic-power-coefficient = <454>;
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cpu-idle-states = <&GOLD_RAIL_OFF>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x40000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cache-size = <0x20000>;
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1946>;
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dynamic-power-coefficient = <454>;
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cpu-idle-states = <&GOLD_RAIL_OFF>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x40000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cache-size = <0x20000>;
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <1946>;
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dynamic-power-coefficient = <454>;
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cpu-idle-states = <&GOLD_RAIL_OFF>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x40000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cache-size = <0x20000>;
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cpu-release-addr = <0x0 0x90000000>;
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capacity-dmips-mhz = <2048>;
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dynamic-power-coefficient = <704>;
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cpu-idle-states = <&GOLD_RAIL_OFF>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x40000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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soc: soc { };
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: hyp_region@80000000 {
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no-map;
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reg = <0x0 0x80000000 0x0 0x600000>;
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};
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xbl_aop_mem: xbl_aop_region@80700000 {
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no-map;
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reg = <0x0 0x80700000 0x0 0x160000>;
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};
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cmd_db: reserved-memory@80860000 {
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compatible = "qcom,cmd-db";
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no-map;
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reg = <0x0 0x80860000 0x0 0x20000>;
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};
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smem_mem: smem_region@80900000 {
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no-map;
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reg = <0x0 0x80900000 0x0 0x200000>;
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};
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removed_mem: removed_region@80b00000 {
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no-map;
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reg = <0x0 0x80b00000 0x0 0x5300000>;
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};
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cpucp_fw_mem: cpucp_fw_region@86200000 {
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no-map;
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reg = <0x0 0x86200000 0x0 0x100000>;
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};
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pil_camera_mem: pil_camera_region@86300000 {
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no-map;
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reg = <0x0 0x86300000 0x0 0x500000>;
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};
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pil_ipa_fw_mem: pil_ipa_fw_region@86800000 {
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no-map;
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reg = <0x0 0x86800000 0x0 0x10000>;
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};
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pil_ipa_gsi_mem: pil_ipa_gsi_region@86810000 {
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no-map;
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reg = <0x0 0x86810000 0x0 0xa000>;
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};
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pil_gpu_mem: pil_gpu_region@8681a000 {
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no-map;
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reg = <0x0 0x8681a000 0x0 0x2000>;
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};
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pil_video_mem: pil_video_region@86900000 {
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no-map;
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reg = <0x0 0x86900000 0x0 0x500000>;
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};
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pil_cvp_mem: pil_cvp_region@86e00000 {
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no-map;
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reg = <0x0 0x86e00000 0x0 0x500000>;
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};
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pil_adsp_mem: pil_adsp_region@87300000 {
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no-map;
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reg = <0x0 0x87300000 0x0 0x2000000>;
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};
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pil_slpi_mem: pil_slpi_region@89300000 {
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no-map;
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reg = <0x0 0x89300000 0x0 0x1500000>;
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};
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pil_modem_mem: modem_region@8a800000 {
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no-map;
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reg = <0x0 0x8a800000 0x0 0xe000000>;
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};
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pil_spss_mem: pil_spss_region@98800000 {
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no-map;
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reg = <0x0 0x98800000 0x0 0x100000>;
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};
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pil_cdsp_mem: pil_cdsp_region@98900000 {
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no-map;
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reg = <0x0 0x98900000 0x0 0x1400000>;
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};
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adsp_mem: adsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0xC00000>;
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};
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sdsp_mem: sdsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x800000>;
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};
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cdsp_secure_heap: cdsp_secure_heap@9b200000 {
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reg = <0x0 0x9b200000 0x0 0x4600000>;
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};
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/* global autoconfigured region for contiguous allocations */
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linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2000000>;
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linux,cma-default;
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};
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};
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chosen { };
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x20000>;
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reg = <0x17a00000 0x10000>, /* GICD */
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<0x17a60000 0x100000>; /* GICR * 8 */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <96000>;
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};
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memtimer: timer@17c20000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17c20000 0x1000>;
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clock-frequency = <500000>;
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frame@17c21000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c21000 0x1000>,
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<0x17c22000 0x1000>;
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};
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frame@17c23000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c23000 0x1000>;
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status = "disabled";
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};
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frame@17c25000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c25000 0x1000>;
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status = "disabled";
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};
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frame@17c27000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c27000 0x1000>;
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status = "disabled";
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};
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frame@17c29000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c29000 0x1000>;
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status = "disabled";
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};
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frame@17c2b000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c2b000 0x1000>;
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status = "disabled";
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};
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frame@17c2d000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x17c2d000 0x1000>;
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status = "disabled";
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};
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};
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qcom,msm-imem@146bf000 {
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compatible = "qcom,msm-imem";
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reg = <0x146bf000 0x1000>;
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ranges = <0x0 0x146bf000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mem_dump_table@10 {
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compatible = "qcom,msm-imem-mem_dump_table";
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reg = <0x10 0x8>;
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};
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restart_reason@65c {
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compatible = "qcom,msm-imem-restart_reason";
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reg = <0x65c 0x4>;
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};
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dload_type@1c {
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compatible = "qcom,msm-imem-dload-type";
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reg = <0x1c 0x4>;
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};
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boot_stats@6b0 {
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compatible = "qcom,msm-imem-boot_stats";
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reg = <0x6b0 0x20>;
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};
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kaslr_offset@6d0 {
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compatible = "qcom,msm-imem-kaslr_offset";
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reg = <0x6d0 0xc>;
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};
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pil@94c {
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compatible = "qcom,msm-imem-pil";
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reg = <0x94c 0xc8>;
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};
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diag_dload@c8 {
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compatible = "qcom,msm-imem-diag-dload";
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reg = <0xc8 0xc8>;
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};
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};
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ipcc_mproc: qcom,ipcc@408000 {
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compatible = "qcom,ipcc";
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reg = <0x408000 0x1000>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#mbox-cells = <2>;
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};
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <38400000>;
|
|
clock-output-names = "xo_board";
|
|
};
|
|
|
|
sleep_clk: sleep-clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32764>;
|
|
};
|
|
};
|
|
|
|
cxo: bi_tcxo {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&xo_board>;
|
|
clock-mult = <1>;
|
|
clock-div = <2>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "bi_tcxo";
|
|
};
|
|
|
|
cxo_a: bi_tcxo_ao {
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&xo_board>;
|
|
clock-mult = <1>;
|
|
clock-div = <2>;
|
|
#clock-cells = <0>;
|
|
clock-output-names = "bi_tcxo_ao";
|
|
};
|
|
|
|
clock_rpmh: qcom,rpmhclk {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "rpmh_clocks";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_aop: qcom,aopclk {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "qdss_clocks";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_gcc: qcom,gcc@100000 {
|
|
compatible = "qcom,lahaina-gcc", "syscon";
|
|
reg = <0x100000 0x1f0000>;
|
|
reg-names = "cc_base";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
clock_videocc: qcom,videocc@abf0000 {
|
|
compatible = "qcom,lahaina-videocc", "syscon";
|
|
reg = <0xabf0000 0x10000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MXA_LEVEL>;
|
|
clock-names = "cfg_ahb_clk";
|
|
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
clock_camcc: qcom,camcc {
|
|
compatible = "qcom,dummycc";
|
|
clock-output-names = "camcc_clocks";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
clock_dispcc: qcom,dispcc@af00000 {
|
|
compatible = "qcom,lahaina-dispcc", "syscon";
|
|
reg = <0xaf00000 0x20000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <&VDD_MM_LEVEL>;
|
|
clock-names = "cfg_ahb_clk";
|
|
clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
clock_gpucc: qcom,gpucc@3d90000 {
|
|
compatible = "qcom,lahaina-gpucc", "syscon";
|
|
reg = <0x3d90000 0x9000>;
|
|
reg-names = "cc_base";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
/* CAM_CC GDSCs */
|
|
cam_cc_bps_gdsc: qcom,gdsc@ad07004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xad07004 0x4>;
|
|
regulator-name = "cam_cc_bps_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MM_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
cam_cc_ife_0_gdsc: qcom,gdsc@ad0a004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xad0a004 0x4>;
|
|
regulator-name = "cam_cc_ife_0_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MM_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
cam_cc_ife_1_gdsc: qcom,gdsc@ad0b004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xad0b004 0x4>;
|
|
regulator-name = "cam_cc_ife_1_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MM_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
cam_cc_ife_2_gdsc: qcom,gdsc@ad0b070 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xad0b070 0x4>;
|
|
regulator-name = "cam_cc_ife_2_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MM_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
cam_cc_ipe_0_gdsc: qcom,gdsc@ad08004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xad08004 0x4>;
|
|
regulator-name = "cam_cc_ipe_0_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MM_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
cam_cc_sbi_gdsc: qcom,gdsc@ad09004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xad09004 0x4>;
|
|
regulator-name = "cam_cc_sbi_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MM_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
cam_cc_titan_top_gdsc: qcom,gdsc@ad0c120 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xad0c120 0x4>;
|
|
regulator-name = "cam_cc_titan_top_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MM_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
/* DISP_CC GDSCs */
|
|
disp_cc_mdss_core_gdsc: qcom,gdsc@af03000 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xaf03000 0x4>;
|
|
regulator-name = "disp_cc_mdss_core_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MM_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
/* GCC GDSCs */
|
|
gcc_pcie_0_gdsc: qcom,gdsc@16b004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x16b004 0x4>;
|
|
regulator-name = "gcc_pcie_0_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
gcc_pcie_1_gdsc: qcom,gdsc@18d004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x18d004 0x4>;
|
|
regulator-name = "gcc_pcie_1_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
gcc_ufs_card_gdsc: qcom,gdsc@175004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x175004 0x4>;
|
|
regulator-name = "gcc_ufs_card_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
gcc_ufs_phy_gdsc: qcom,gdsc@177004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x177004 0x4>;
|
|
regulator-name = "gcc_ufs_phy_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
gcc_usb30_prim_gdsc: qcom,gdsc@10f004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x10f004 0x4>;
|
|
regulator-name = "gcc_usb30_prim_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
gcc_usb30_sec_gdsc: qcom,gdsc@110004 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x110004 0x4>;
|
|
regulator-name = "gcc_usb30_sec_gdsc";
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x17d050 0x4>;
|
|
regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <500>;
|
|
};
|
|
|
|
gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x17d058 0x4>;
|
|
regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <500>;
|
|
};
|
|
|
|
gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x17d054 0x4>;
|
|
regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <500>;
|
|
};
|
|
|
|
gcc_hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x17d06c 0x4>;
|
|
regulator-name = "gcc_hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc";
|
|
qcom,no-status-check-on-disable;
|
|
qcom,gds-timeout = <500>;
|
|
};
|
|
|
|
/* GPU_CC GDSCs */
|
|
gpu_cc_cx_hw_ctrl: syscon@3d91540 {
|
|
compatible = "syscon";
|
|
reg = <0x3d91540 0x4>;
|
|
};
|
|
|
|
gpu_cc_cx_gdsc: qcom,gdsc@3d9106c {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x3d9106c 0x4>;
|
|
regulator-name = "gpu_cc_cx_gdsc";
|
|
hw-ctrl-addr = <&gpu_cc_cx_hw_ctrl>;
|
|
parent-supply = <&VDD_CX_LEVEL>;
|
|
qcom,no-status-check-on-disable;
|
|
qcom,clk-dis-wait-val = <8>;
|
|
qcom,gds-timeout = <500>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
gpu_cc_gx_domain_addr: syscon@3d9158c {
|
|
compatible = "syscon";
|
|
reg = <0x3d9158c 0x4>;
|
|
};
|
|
|
|
gpu_cc_gx_sw_reset: syscon@3d91008 {
|
|
compatible = "syscon";
|
|
reg = <0x3d91008 0x4>;
|
|
};
|
|
|
|
gpu_cc_gx_gdsc: qcom,gdsc@3d9100c {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0x3d9100c 0x4>;
|
|
regulator-name = "gpu_cc_gx_gdsc";
|
|
domain-addr = <&gpu_cc_gx_domain_addr>;
|
|
sw-reset = <&gpu_cc_gx_sw_reset>;
|
|
parent-supply = <&VDD_GFX_LEVEL>;
|
|
vdd_parent-supply = <&VDD_GFX_LEVEL>;
|
|
qcom,reset-aon-logic;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
/* VIDEO_CC GDSCs */
|
|
video_cc_mvs0_gdsc: qcom,gdsc@abf0d18 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xabf0d18 0x4>;
|
|
regulator-name = "video_cc_mvs0_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MM_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
video_cc_mvs0c_gdsc: qcom,gdsc@abf0bf8 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xabf0bf8 0x4>;
|
|
regulator-name = "video_cc_mvs0c_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MM_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
video_cc_mvs1_gdsc: qcom,gdsc@abf0d98 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xabf0d98 0x4>;
|
|
regulator-name = "video_cc_mvs1_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MM_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
video_cc_mvs1c_gdsc: qcom,gdsc@abf0c98 {
|
|
compatible = "qcom,gdsc";
|
|
reg = <0xabf0c98 0x4>;
|
|
regulator-name = "video_cc_mvs1c_gdsc";
|
|
clock-names = "ahb_clk";
|
|
clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
|
|
parent-supply = <&VDD_MM_LEVEL>;
|
|
vdd_parent-supply = <&VDD_MM_LEVEL>;
|
|
qcom,retain-regs;
|
|
};
|
|
|
|
cache-controller@9200000 {
|
|
compatible = "qcom,lahaina-llcc", "qcom,llcc-v2";
|
|
reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
|
|
reg-names = "llcc_base", "llcc_broadcast_base";
|
|
cap-based-alloc-and-pwr-collapse;
|
|
};
|
|
|
|
qcom_scm {
|
|
compatible = "qcom,secure-chan-manager";
|
|
};
|
|
|
|
qtee_shmbridge {
|
|
compatible = "qcom,tee-shared-memory-bridge";
|
|
};
|
|
|
|
qcom-secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
};
|
|
|
|
qcom,chd {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "core";
|
|
qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058
|
|
0x18040058 0x18050058 0x18060058 0x18070058>;
|
|
qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060
|
|
0x18040060 0x18050060 0x18060060 0x18070060>;
|
|
};
|
|
|
|
aggre1_noc: interconnect@16e0000 {
|
|
compatible = "qcom,lahaina-aggre1_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
aggre2_noc: interconnect@1700000 {
|
|
compatible = "qcom,lahaina-aggre2_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
config_noc: interconnect@1500000 {
|
|
compatible = "qcom,lahaina-config_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
dc_noc: interconnect@14e0000 {
|
|
compatible = "qcom,lahaina-dc_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
gem_noc: interconnect@1380000 {
|
|
compatible = "qcom,lahaina-gem_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
lpass_ag_noc: interconnect@1480000 {
|
|
compatible = "qcom,lahaina-lpass_ag_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mc_virt: interconnect@1580000 {
|
|
compatible = "qcom,lahaina-mc_virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mmss_noc: interconnect@1740000 {
|
|
compatible = "qcom,lahaina-mmss_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
nsp_noc: interconnect@1750000 {
|
|
compatible = "qcom,lahaina-nsp_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
system_noc: interconnect@1620000 {
|
|
compatible = "qcom,lahaina-system_noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
pil_scm_pas {
|
|
compatible = "qcom,pil-tz-scm-pas";
|
|
interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
|
|
};
|
|
|
|
qcom,msm-rtb {
|
|
compatible = "qcom,msm-rtb";
|
|
qcom,rtb-size = <0x100000>;
|
|
};
|
|
|
|
ufsphy_mem: ufsphy_mem@1d87000 {
|
|
reg = <0x1d87000 0xe10>;
|
|
reg-names = "phy_mem";
|
|
#phy-cells = <0>;
|
|
|
|
lanes-per-direction = <2>;
|
|
clock-names = "ref_clk_src",
|
|
"ref_aux_clk";
|
|
clocks = <&clock_rpmh RPMH_CXO_CLK>,
|
|
<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;
|
|
|
|
resets = <&ufshc_mem 0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ufshc_mem: ufshc@1d84000 {
|
|
compatible = "qcom,ufshc";
|
|
reg = <0x1d84000 0x3000>;
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&ufsphy_mem>;
|
|
phy-names = "ufsphy";
|
|
#reset-cells = <1>;
|
|
|
|
lanes-per-direction = <2>;
|
|
dev-ref-clk-freq = <0>; /* 19.2 MHz */
|
|
|
|
clock-names =
|
|
"core_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro",
|
|
"core_clk_ice",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk",
|
|
"rx_lane1_sync_clk";
|
|
clocks =
|
|
<&clock_gcc GCC_UFS_PHY_AXI_CLK>,
|
|
<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&clock_gcc GCC_UFS_PHY_AHB_CLK>,
|
|
<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
|
|
<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,
|
|
<&clock_rpmh RPMH_CXO_CLK>,
|
|
<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
|
<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
|
|
<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
|
|
freq-table-hz =
|
|
<75000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<75000000 300000000>,
|
|
<75000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>;
|
|
|
|
reset-gpios = <&tlmm 203 GPIO_ACTIVE_LOW>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
kryo-erp {
|
|
compatible = "arm,arm64-kryo-cpu-erp";
|
|
interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "l1-l2-faultirq","l3-scu-faultirq";
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
smem: qcom,smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_mem>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
qmp_aop: qcom,qmp-aop@c300000 {
|
|
compatible = "qcom,qmp-mbox";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "aop_qmp";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_AOP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
reg = <0xc300000 0x400>;
|
|
reg-names = "msgram";
|
|
|
|
label = "aop";
|
|
qcom,early-boot;
|
|
priority = <0>;
|
|
mbox-desc-offset = <0x0>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
aop-msg-client {
|
|
compatible = "qcom,debugfs-qmp-client";
|
|
mboxes = <&qmp_aop 0>;
|
|
mbox-names = "aop";
|
|
};
|
|
|
|
qcom,smp2p_sleepstate {
|
|
compatible = "qcom,smp2p-sleepstate";
|
|
qcom,smem-states = <&sleepstate_smp2p_out 0>;
|
|
interrupt-parent = <&sleepstate_smp2p_in>;
|
|
interrupts = <0 0>;
|
|
interrupt-names = "smp2p-sleepstate-in";
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,lahaina-pdc";
|
|
reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
|
|
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>,
|
|
<59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>,
|
|
<69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>,
|
|
<156 716 12>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
apps_rsc: rsc@18200000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x18200000 0x10000>,
|
|
<0x18210000 0x10000>,
|
|
<0x18220000 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>,
|
|
<CONTROL_TCS 1>;
|
|
|
|
apps_bcm_voter: bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
|
|
system_pm {
|
|
compatible = "qcom,system-pm";
|
|
};
|
|
};
|
|
|
|
disp_rsc: rsc@af20000 {
|
|
status = "disabled";
|
|
label = "disp_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xaf20000 0x10000>;
|
|
reg-names = "drv-0";
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,tcs-offset = <0x1c00>;
|
|
qcom,drv-id = <0>;
|
|
qcom,tcs-config = <ACTIVE_TCS 0>,
|
|
<SLEEP_TCS 1>,
|
|
<WAKE_TCS 1>,
|
|
<CONTROL_TCS 0>;
|
|
};
|
|
|
|
qcom,msm-cdsp-loader {
|
|
compatible = "qcom,cdsp-loader";
|
|
qcom,proc-img-to-load = "cdsp";
|
|
};
|
|
|
|
qcom,msm-adsprpc-mem {
|
|
compatible = "qcom,msm-adsprpc-mem-region";
|
|
memory-region = <&adsp_mem>;
|
|
restrict-access;
|
|
};
|
|
|
|
msm_fastrpc: qcom,msm_fastrpc {
|
|
compatible = "qcom,msm-fastrpc-compute";
|
|
qcom,adsp-remoteheap-vmid = <22 37>;
|
|
qcom,fastrpc-adsp-audio-pdr;
|
|
qcom,fastrpc-adsp-sensors-pdr;
|
|
qcom,rpc-latency-us = <235>;
|
|
|
|
qcom,msm_fastrpc_compute_cb1 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x2161 0x0400>,
|
|
<&apps_smmu 0x1181 0x0420>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb2 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x2142 0x04A0>,
|
|
<&apps_smmu 0x1102 0x04A0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb3 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x2143 0x14A0>,
|
|
<&apps_smmu 0x1103 0x04E0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb4 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x0144 0x2420>,
|
|
<&apps_smmu 0x1184 0x0460>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb5 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x2165 0x0480>,
|
|
<&apps_smmu 0x1105 0x04E0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb6 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x0126 0x34C0>,
|
|
<&apps_smmu 0x1186 0x2400>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb7 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x2147 0x0420>,
|
|
<&apps_smmu 0x1187 0x2420>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb8 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x0148 0x3420>,
|
|
<&apps_smmu 0x1108 0x24A0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb9 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
qcom,secure-context-bank;
|
|
iommus = <&apps_smmu 0x0149 0x34A0>,
|
|
<&apps_smmu 0x1109 0x04E0>;
|
|
qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb10 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x1803 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb11 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x1804 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb12 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x1805 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb13 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "sdsprpc-smd";
|
|
iommus = <&apps_smmu 0x0541 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb14 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "sdsprpc-smd";
|
|
iommus = <&apps_smmu 0x0542 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
dma-coherent;
|
|
};
|
|
|
|
qcom,msm_fastrpc_compute_cb15 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "sdsprpc-smd";
|
|
iommus = <&apps_smmu 0x0543 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
|
qcom,iommu-faults = "stall-disable";
|
|
shared-cb = <4>;
|
|
dma-coherent;
|
|
};
|
|
};
|
|
|
|
wdog: qcom,wdt@17c10000{
|
|
compatible = "qcom,msm-watchdog";
|
|
reg = <0x17c10000 0x1000>;
|
|
reg-names = "wdt-base";
|
|
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,bark-time = <11000>;
|
|
qcom,pet-time = <9360>;
|
|
qcom,ipi-ping;
|
|
qcom,wakeup-enable;
|
|
};
|
|
|
|
qcom,glink {
|
|
compatible = "qcom,glink";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
glink_modem: modem {
|
|
qcom,remote-pid = <1>;
|
|
transport = "smem";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "mpss_smem";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_MPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "modem";
|
|
qcom,glink-label = "mpss";
|
|
|
|
qcom,modem_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,low-latency;
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,modem_ds {
|
|
qcom,glink-channels = "DS";
|
|
qcom,intents = <0x4000 0x2>;
|
|
};
|
|
|
|
qcom,modem_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_adsp>,
|
|
<&glink_slpi>,
|
|
<&glink_spss>;
|
|
};
|
|
};
|
|
|
|
glink_adsp: adsp {
|
|
qcom,remote-pid = <2>;
|
|
transport = "smem";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "adsp_smem";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_LPASS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "adsp";
|
|
qcom,glink-label = "lpass";
|
|
|
|
qcom,adsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,adsp_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_slpi>,
|
|
<&glink_modem>;
|
|
};
|
|
};
|
|
|
|
glink_slpi: dsps {
|
|
qcom,remote-pid = <3>;
|
|
transport = "smem";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "dsps_smem";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_SLPI
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "slpi";
|
|
qcom,glink-label = "dsps";
|
|
|
|
qcom,slpi_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,low-latency;
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,slpi_glink_ssr {
|
|
qcom,glink-channels = "glink_ssr";
|
|
qcom,notify-edges = <&glink_adsp>,
|
|
<&glink_modem>;
|
|
};
|
|
};
|
|
|
|
glink_cdsp: cdsp {
|
|
qcom,remote-pid = <5>;
|
|
transport = "smem";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "dsps_smem";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_CDSP
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "cdsp";
|
|
qcom,glink-label = "cdsp";
|
|
|
|
qcom,cdsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
};
|
|
|
|
glink_spss: spss {
|
|
qcom,remote-pid = <8>;
|
|
transport = "spss";
|
|
mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
|
mbox-names = "spss_spss";
|
|
interrupt-parent = <&ipcc_mproc>;
|
|
interrupts = <IPCC_CLIENT_SPSS
|
|
IPCC_MPROC_SIGNAL_GLINK_QMP
|
|
IRQ_TYPE_EDGE_RISING>;
|
|
|
|
reg = <0x1885008 0x8>,
|
|
<0x1885010 0x4>;
|
|
reg-names = "qcom,spss-addr",
|
|
"qcom,spss-size";
|
|
|
|
label = "spss";
|
|
qcom,glink-label = "spss";
|
|
};
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-apr-apps2 {
|
|
qcom,glinkpkt-edge = "adsp";
|
|
qcom,glinkpkt-ch-name = "apr_apps2";
|
|
qcom,glinkpkt-dev-name = "apr_apps2";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
};
|
|
|
|
qcom,lpass@17300000 {
|
|
compatible = "qcom,pil-tz-generic";
|
|
reg = <0x17300000 0x00100>;
|
|
|
|
vdd_cx-supply = <&VDD_LPI_CX_LEVEL>;
|
|
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
vdd_mx-supply = <&VDD_LPI_MX_LEVEL>;
|
|
qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
qcom,proxy-reg-names = "vdd_cx","vdd_mx";
|
|
|
|
clocks = <&clock_rpmh RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
qcom,proxy-clock-names = "xo";
|
|
|
|
qcom,pas-id = <1>;
|
|
qcom,proxy-timeout-ms = <10000>;
|
|
qcom,smem-id = <423>;
|
|
qcom,sysmon-id = <1>;
|
|
qcom,ssctl-instance-id = <0x14>;
|
|
qcom,firmware-name = "adsp";
|
|
memory-region = <&pil_adsp_mem>;
|
|
qcom,signal-aop;
|
|
qcom,complete-ramdump;
|
|
|
|
/* Inputs from lpass */
|
|
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&adsp_smp2p_in 0 0>,
|
|
<&adsp_smp2p_in 2 0>,
|
|
<&adsp_smp2p_in 1 0>,
|
|
<&adsp_smp2p_in 3 0>;
|
|
|
|
interrupt-names = "qcom,wdog",
|
|
"qcom,err-fatal",
|
|
"qcom,proxy-unvote",
|
|
"qcom,err-ready",
|
|
"qcom,stop-ack";
|
|
|
|
/* Outputs to lpass */
|
|
qcom,smem-states = <&adsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "qcom,force-stop";
|
|
|
|
mboxes = <&qmp_aop 0>;
|
|
mbox-names = "adsp-pil";
|
|
};
|
|
|
|
qcom,turing@0x98900000 {
|
|
compatible = "qcom,pil-tz-generic";
|
|
reg = <0x98900000 0x1400000>;
|
|
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
|
vdd_mx-supply = <&VDD_MXC_LEVEL>;
|
|
qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
|
qcom,proxy-reg-names = "vdd_cx","vdd_mx";
|
|
|
|
clocks = <&clock_rpmh RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
qcom,proxy-clock-names = "xo";
|
|
|
|
qcom,pas-id = <18>;
|
|
qcom,proxy-timeout-ms = <10000>;
|
|
qcom,smem-id = <601>;
|
|
qcom,sysmon-id = <7>;
|
|
qcom,ssctl-instance-id = <0x17>;
|
|
qcom,firmware-name = "cdsp";
|
|
memory-region = <&pil_cdsp_mem>;
|
|
qcom,complete-ramdump;
|
|
|
|
interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
|
|
|
|
/* Inputs from turing */
|
|
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&cdsp_smp2p_in 0 0>,
|
|
<&cdsp_smp2p_in 2 0>,
|
|
<&cdsp_smp2p_in 1 0>,
|
|
<&cdsp_smp2p_in 3 0>;
|
|
|
|
interrupt-names = "qcom,wdog",
|
|
"qcom,err-fatal",
|
|
"qcom,proxy-unvote",
|
|
"qcom,err-ready",
|
|
"qcom,stop-ack";
|
|
|
|
/* Outputs to turing */
|
|
qcom,smem-states = <&cdsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "qcom,force-stop";
|
|
|
|
};
|
|
|
|
|
|
qcom,venus@aab0000 {
|
|
compatible = "qcom,pil-tz-generic";
|
|
reg = <0xaab0000 0x2000>;
|
|
|
|
vdd-supply = <&video_cc_mvs0c_gdsc>;
|
|
qcom,proxy-reg-names = "vdd";
|
|
qcom,complete-ramdump;
|
|
|
|
clocks = <&clock_videocc VIDEO_CC_XO_CLK>,
|
|
<&clock_videocc VIDEO_CC_MVS0C_CLK>,
|
|
<&clock_videocc VIDEO_CC_AHB_CLK>;
|
|
clock-names = "xo", "core", "ahb";
|
|
qcom,proxy-clock-names = "xo", "core", "ahb";
|
|
|
|
qcom,core-freq = <200000000>;
|
|
qcom,ahb-freq = <200000000>;
|
|
|
|
qcom,pas-id = <9>;
|
|
interconnect-names = "pil-venus";
|
|
interconnects = <&mmss_noc MASTER_VIDEO_P0
|
|
&mc_virt SLAVE_EBI1>;
|
|
qcom,proxy-timeout-ms = <100>;
|
|
qcom,firmware-name = "venus";
|
|
memory-region = <&pil_video_mem>;
|
|
};
|
|
|
|
qcom,msm_gsi {
|
|
compatible = "qcom,msm_gsi";
|
|
};
|
|
|
|
qcom,rmnet-ipa {
|
|
compatible = "qcom,rmnet-ipa3";
|
|
qcom,rmnet-ipa-ssr;
|
|
qcom,ipa-platform-type-msm;
|
|
qcom,ipa-advertise-sg-support;
|
|
qcom,ipa-napi-enable;
|
|
};
|
|
|
|
qcom,ipa_fws {
|
|
compatible = "qcom,pil-tz-generic";
|
|
qcom,pas-id = <0xf>;
|
|
qcom,firmware-name = "ipa_fws";
|
|
qcom,pil-force-shutdown;
|
|
memory-region = <&pil_ipa_gsi_mem>;
|
|
};
|
|
|
|
ipa_hw: qcom,ipa@1e00000 {
|
|
compatible = "qcom,ipa";
|
|
mboxes = <&qmp_aop 0>;
|
|
reg =
|
|
<0x1e00000 0x84000>,
|
|
<0x1e04000 0x23000>;
|
|
reg-names = "ipa-base", "gsi-base";
|
|
interrupts =
|
|
<0 654 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 432 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ipa-irq", "gsi-irq";
|
|
qcom,ipa-hw-ver = <19>; /* IPA core version = IPAv4.9 */
|
|
qcom,ipa-hw-mode = <0>;
|
|
qcom,platform-type = <1>; /* MSM platform */
|
|
qcom,ee = <0>;
|
|
qcom,use-ipa-tethering-bridge;
|
|
qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */
|
|
qcom,modem-cfg-emb-pipe-flt;
|
|
qcom,ipa-wdi3-over-gsi;
|
|
qcom,arm-smmu;
|
|
qcom,smmu-fast-map;
|
|
qcom,bandwidth-vote-for-ipa;
|
|
qcom,use-64-bit-dma-mask;
|
|
qcom,ipa-endp-delay-wa;
|
|
qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
|
|
"TURBO";
|
|
qcom,throughput-threshold = <600 2500 5000>;
|
|
qcom,scaling-exceptions = <>;
|
|
|
|
qcom,entire-ipa-block-size = <0x100000>;
|
|
qcom,testbus-collection-on-crash;
|
|
qcom,non-tn-collection-on-crash;
|
|
qcom,ram-collection-on-crash;
|
|
qcom,secure-debug-check-action = <0>;
|
|
|
|
ipa_smmu_ap: ipa_smmu_ap {
|
|
compatible = "qcom,ipa-smmu-ap-cb";
|
|
iommus = <&apps_smmu 0x5C0 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
|
|
qcom,additional-mapping =
|
|
/* modem tables in IMEM */
|
|
<0x146BD000 0x146BD000 0x2000>;
|
|
dma-coherent;
|
|
qcom,iommu-dma = "fastmap";
|
|
};
|
|
|
|
ipa_smmu_wlan: ipa_smmu_wlan {
|
|
compatible = "qcom,ipa-smmu-wlan-cb";
|
|
iommus = <&apps_smmu 0x5C1 0x0>;
|
|
qcom,iommu-dma = "fastmap";
|
|
};
|
|
|
|
ipa_smmu_uc: ipa_smmu_uc {
|
|
compatible = "qcom,ipa-smmu-uc-cb";
|
|
iommus = <&apps_smmu 0x5C2 0x0>;
|
|
qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
|
|
qcom,iommu-dma = "fastmap";
|
|
};
|
|
|
|
ipa_smmu_11ad: ipa_smmu_11ad {
|
|
compatible = "qcom,ipa-smmu-11ad-cb";
|
|
iommus = <&apps_smmu 0x5C3 0x0>;
|
|
dma-coherent;
|
|
qcom,shared-cb;
|
|
qcom,iommu-group = <>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "lahaina-regulators.dtsi"
|
|
#include "lahaina-pinctrl.dtsi"
|
|
#include "lahaina-smp2p.dtsi"
|
|
#include "lahaina-ion.dtsi"
|
|
#include "msm-arm-smmu-lahaina.dtsi"
|
|
#include "lahaina-usb.dtsi"
|
|
#include "lahaina-pm.dtsi"
|
|
#include "lahaina-qupv3.dtsi"
|