Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
2
0
Fork 0
mirror of https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees synced 2026-02-01 05:00:27 +00:00
Code Issues Packages Projects Releases Wiki Activity

ARM: dts: msm: Add devicetree snapshot for Waipio Support

Browse Source 
Add devicetree files for supporting waipio platform on msm-kalama branch
with snapshot merge of msm-5.10 devicetree at commit <c8b773e> (Merge "ARM:
dts: msm: Enable stats driver for diwali").

Change-Id: I887faca72435ac45605a330ce0520d6b8b6f26b8
This commit is contained in:
Jeevan Shriram
2021-08-16 22:55:20 -07:00
parent 42b0ee42db
commit 052669f651
110 changed files with 24833 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

37
qcom/Makefile
View File

@@ -1,4 +1,41 @@
# add-overlay defines the target with following naming convention:
# <base>-<board>-dtbs = base.dtb board.dtbo
#
# Combined dtb target is also generated using the fdt_overlay tool.
# dtb-y += <base>-<board>.dtb
add-overlays = $(foreach o,$1,$(foreach b,$2,$(eval $(basename $b)-$(basename $o)-dtbs = $b $o) $(basename $b)-$(basename $o).dtb))
WAIPIO_BASE_DTB += waipio.dtb waipio-v2.dtb
WAIPIO_APQ_BASE_DTB += waipiop.dtb waipiop-v2.dtb
WAIPIO_BOARDS += \
waipio-rumi-overlay.dtbo \
waipio-mtp-pm8008-overlay.dtbo \
waipio-cdp-pm8008-overlay.dtbo \
waipio-qrd-pm8008-overlay.dtbo \
waipio-atp-pm8008-overlay.dtbo \
waipio-mtp-pm8010-overlay.dtbo \
waipio-cdp-pm8010-overlay.dtbo \
waipio-qrd-pm8010-overlay.dtbo \
waipio-qrd-pm8010-2s-overlay.dtbo \
waipio-atp-pm8010-overlay.dtbo
NOAPQ_WAIPIO_BOARDS += \
waipiop-hdk-pm8010-overlay.dtbo \
waipio-lemur-mtp-pm8008-overlay.dtbo \
waipio-lemur-mtp-pm8010-overlay.dtbo \
waipio-lemur-cdp-pm8008-overlay.dtbo \
waipio-lemur-cdp-pm8010-overlay.dtbo \
waipio-kiwi-mtp-pm8008-overlay.dtbo \
waipio-kiwi-mtp-pm8010-overlay.dtbo
dtb-$(CONFIG_ARCH_WAIPIO) += \
$(call add-overlays, $(WAIPIO_BOARDS) $(NOAPQ_WAIPIO_BOARDS),$(WAIPIO_BASE_DTB))\
$(call add-overlays, $(WAIPIO_BOARDS) $(APQ_WAIPIO_BOARDS),$(WAIPIO_APQ_BASE_DTB))
dtb-$(CONFIG_ARCH_KALAMA) += kalama-rumi.dtb \
kalama-mtp.dtb \
kalama-cdp.dtb \

31
qcom/ipcc-test.dtsi Normal file
View File

@@ -0,0 +1,31 @@
#include <dt-bindings/soc/qcom,ipcc.h>
&soc {
ipcc_self_ping_apss: ipcc-self-ping-apss {
compatible = "qcom,ipcc-self-ping";
interrupts-extended = <&ipcc_mproc IPCC_CLIENT_APSS
IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ipcc_mproc IPCC_CLIENT_APSS IPCC_MPROC_SIGNAL_SMP2P>;
};
ipcc_self_ping_cdsp: ipcc-self-ping-cdsp {
compatible = "qcom,ipcc-self-ping";
interrupts-extended = <&ipcc_mproc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_PING>;
};
ipcc_self_ping_adsp: ipcc-self-ping-adsp {
compatible = "qcom,ipcc-self-ping";
interrupts-extended = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_PING>;
};
ipcc_self_ping_slpi: ipcc-self-ping-slpi {
compatible = "qcom,ipcc-self-ping";
interrupts-extended = <&ipcc_mproc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>;
mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_PING>;
};
};

31
qcom/msm-arm-smmu-waipio-vm.dtsi Executable file
View File

@@ -0,0 +1,31 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
vm-config {
vdevices {
vsmmu@15000000 {
vdevice-type = "vsmmu-v2";
smmu-handle = <0x15000000>;
num-cbs = <0x2>;
num-smrs = <0x3>;
patch = "/soc/apps-smmu@15000000";
};
};
};
};
&soc {
apps_smmu: apps-smmu@15000000 {
/*
* reg, #global-interrupts & interrupts properties will
* be added dynamically by bootloader.
*/
compatible = "qcom,qsmmu-v500", "qcom,virt-smmu";
#iommu-cells = <2>;
qcom,use-3-lvl-tables;
dma-coherent;
qcom,actlr =
<0x2803 0x0400 0x00000001>,
<0x2804 0x0402 0x00000001>;
};
};

409
qcom/msm-arm-smmu-waipio.dtsi Normal file
View File

@@ -0,0 +1,409 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
&soc {
kgsl_smmu: kgsl-smmu@3da0000 {
compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
reg = <0x3DA0000 0x40000>,
<0x3DE6000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,skip-init;
qcom,use-3-lvl-tables;
qcom,num-context-banks-override = <0x15>;
qcom,num-smr-override = <0x18>;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
dma-coherent;
qcom,regulator-names = "vdd";
vdd-supply = <&gpu_cc_cx_gdsc>;
clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
<&clock_gpucc GPU_CC_HUB_CX_INT_CLK>,
<&clock_gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&clock_gpucc GPU_CC_AHB_CLK>;
clock-names =
"gpu_cc_cx_gmu",
"gpu_cc_hub_cx_int",
"gpu_cc_hlos1_vote_gpu_smmu",
"gcc_gpu_memnoc_gfx",
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb";
qcom,actlr =
/* All CBs of GFX: +15 deep PF */
<0x000 0x3ff 0x32B>,
<0x400 0x3ff 0x32B>;
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
gfx_0_tbu: gfx_0_tbu@3de9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x3de9000 0x1000>,
<0x3de6200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
};
gfx_1_tbu: gfx_1_tbu@3ded000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x3ded000 0x1000>,
<0x3de6208 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x400 0x400>;
};
};
apps_smmu: apps-smmu@15000000 {
compatible = "qcom,qsmmu-v500";
reg = <0x15000000 0x100000>,
<0x151ce000 0x20>;
reg-names = "base", "tcu-base";
#iommu-cells = <2>;
qcom,skip-init;
qcom,use-3-lvl-tables;
qcom,num-context-banks-override = <0x4e>;
qcom,num-smr-override = <0x78>;
qcom,handoff-smrs = <3>;
#global-interrupts = <1>;
#size-cells = <1>;
#address-cells = <1>;
ranges;
dma-coherent;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
/* Autogenerated */
qcom,actlr =
<0x0001 0x24e0 0x00000001>,
<0x0001 0x0ce0 0x00000001>,
<0x0001 0x1420 0x00000303>,
<0x0002 0x3420 0x00000303>,
<0x0004 0x3560 0x00000303>,
<0x0005 0x3420 0x00000303>,
<0x0006 0x3560 0x00000303>,
<0x0007 0x3560 0x00000303>,
<0x0008 0x3560 0x00000303>,
<0x0009 0x3560 0x00000303>,
<0x000c 0x3560 0x00000303>,
<0x000d 0x3560 0x00000303>,
<0x000e 0x3560 0x00000303>,
<0x000f 0x3560 0x00000303>,
<0x0121 0x2c80 0x00000001>,
<0x0165 0x2400 0x00000303>,
<0x0800 0x0460 0x00000001>,
<0x0880 0x0400 0x00000001>,
<0x1000 0x0400 0x00000303>,
<0x1003 0x2520 0x00000303>,
<0x100a 0x0400 0x00000303>,
<0x100b 0x0420 0x00000303>,
<0x2000 0x0420 0x00000001>,
<0x2002 0x0500 0x00000001>,
<0x2003 0x0560 0x00000303>,
<0x2040 0x0420 0x00000001>,
<0x2042 0x1520 0x00000303>,
<0x206b 0x1500 0x00000303>,
<0x2080 0x0400 0x00000001>,
<0x20a0 0x0400 0x00000001>,
<0x20c0 0x0400 0x00000001>,
<0x20e0 0x0400 0x00000001>,
<0x2100 0x0420 0x00000001>,
<0x2101 0x0400 0x00000001>,
<0x2161 0x0400 0x00000303>,
<0x2180 0x0400 0x00000103>,
<0x2181 0x0404 0x00000103>,
<0x2182 0x0400 0x00000103>,
<0x2183 0x0400 0x00000103>,
<0x2184 0x0400 0x00000103>,
<0x2187 0x0400 0x00000103>,
<0x2800 0x0402 0x00000001>,
<0x2801 0x0000 0x00000001>,
<0x2803 0x0000 0x00000001>,
<0x2806 0x0400 0x00000001>,
<0x2c01 0x0000 0x00000001>,
<0x2c03 0x0000 0x00000001>;
anoc_1_tbu: anoc_1_tbu@151d1000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151d1000 0x1000>,
<0x151ce200 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x0 0x400>;
qcom,micro-idle;
};
anoc_2_tbu: anoc_2_tbu@151d5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151d5000 0x1000>,
<0x151ce208 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x400 0x400>;
qcom,micro-idle;
};
cam_0_tbu: cam_0_tbu@151d9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151d9000 0x1000>,
<0x151ce210 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x800 0x400>;
qcom,micro-idle;
};
cam_1_tbu: cam_1_tbu@151dd000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151dd000 0x1000>,
<0x151ce218 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0xc00 0x400>;
qcom,micro-idle;
};
compute_1_tbu: compute_1_tbu@151e1000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151e1000 0x1000>,
<0x151ce220 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1000 0x400>;
qcom,micro-idle;
};
compute_0_tbu: compute_0_tbu@151e5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151e5000 0x1000>,
<0x151ce228 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1400 0x400>;
qcom,micro-idle;
};
lpass_tbu: lpass_tbu@151e9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151e9000 0x1000>,
<0x151ce230 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1800 0x400>;
qcom,micro-idle;
};
pcie_tbu: pcie_tbu@151ed000 {
status = "disabled";
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151ed000 0x1000>,
<0x151ce238 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x1c00 0x400>;
qcom,micro-idle;
};
sf_0_tbu: sf_0_tbu@151f1000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151f1000 0x1000>,
<0x151ce240 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x2000 0x400>;
qcom,micro-idle;
};
sf_1_tbu: sf_1_tbu@151f5000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151f5000 0x1000>,
<0x151ce248 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x2400 0x400>;
qcom,micro-idle;
};
mdp_0_tbu: mdp_0_tbu@151f9000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151f9000 0x1000>,
<0x151ce250 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x2800 0x400>;
qcom,micro-idle;
};
mdp_1_tbu: mdp_1_tbu@151fd000 {
compatible = "qcom,qsmmuv500-tbu";
reg = <0x151fd000 0x1000>,
<0x151ce258 0x8>;
reg-names = "base", "status-reg";
qcom,stream-id-range = <0x2c00 0x400>;
qcom,micro-idle;
};
};
dma_dev@0x0 {
compatible = "qcom,iommu-dma";
memory-region = <&system_cma>;
};
iommu_test_device {
compatible = "qcom,iommu-debug-test";
usecase0_apps {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
};
usecase1_apps_fastmap {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
qcom,iommu-dma = "fastmap";
};
usecase2_apps_atomic {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
qcom,iommu-dma = "atomic";
};
usecase3_apps_dma {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e1 0>;
dma-coherent;
};
usecase4_apps_secure {
compatible = "qcom,iommu-debug-usecase";
iommus = <&apps_smmu 0x7e0 0>;
qcom,iommu-dma = "atomic";
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
};
usecase5_kgsl {
compatible = "qcom,iommu-debug-usecase";
iommus = <&kgsl_smmu 0x7 0x400>;
};
usecase6_kgsl_dma {
compatible = "qcom,iommu-debug-usecase";
iommus = <&kgsl_smmu 0x407 0x400>;
dma-coherent;
};
};
};

26
qcom/msm-rdbg.dtsi Normal file
View File

@@ -0,0 +1,26 @@
&soc {
/* smp2p information */
qcom,smp2p_interrupt_rdbg_2_out {
compatible = "qcom,smp2p-interrupt-rdbg-2-out";
qcom,smem-states = <&smp2p_rdbg2_out 0>;
qcom,smem-state-names = "rdbg-smp2p-out";
};
qcom,smp2p_interrupt_rdbg_2_in {
compatible = "qcom,smp2p-interrupt-rdbg-2-in";
interrupts-extended = <&smp2p_rdbg2_in 0 0>;
interrupt-names = "rdbg-smp2p-in";
};
qcom,smp2p_interrupt_rdbg_5_out {
compatible = "qcom,smp2p-interrupt-rdbg-5-out";
qcom,smem-states = <&smp2p_rdbg5_out 0>;
qcom,smem-state-names = "rdbg-smp2p-out";
};
qcom,smp2p_interrupt_rdbg_5_in {
compatible = "qcom,smp2p-interrupt-rdbg-5-in";
interrupts-extended = <&smp2p_rdbg5_in 0 0>;
interrupt-names = "rdbg-smp2p-in";
};
};

61
qcom/pm8350.dtsi Normal file
View File

@@ -0,0 +1,61 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pm8350@1 {
compatible = "qcom,spmi-pmic";
reg = <1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8350_tz: qcom,temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8350_gpios: pinctrl@8800 {
compatible = "qcom,pm8350-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
&thermal_zones {
pm8350_temp_alarm: pm8350_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8350_tz>;
trips {
pm8350_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8350_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
pm8350_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};

385
qcom/pm8350b.dtsi Normal file
View File

@@ -0,0 +1,385 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/input/qcom,hv-haptics.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pm8350b@3 {
compatible = "qcom,spmi-pmic";
reg = <3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8350b_tz: qcom,temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8350b_pbs2: qcom,pbs@1900 {
compatible = "qcom,qpnp-pbs";
reg = <0x1900>;
};
pm8350b_gpios: pinctrl@8800 {
compatible = "qcom,pm8350b-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pm8350b_bcl: bcl@4700 {
compatible = "qcom,bcl-v5";
reg = <0x4700 0x100>;
interrupts = <0x3 0x47 0x0 IRQ_TYPE_NONE>,
<0x3 0x47 0x1 IRQ_TYPE_NONE>,
<0x3 0x47 0x2 IRQ_TYPE_NONE>;
interrupt-names = "bcl-lvl0",
"bcl-lvl1",
"bcl-lvl2";
qcom,pmic7-threshold;
#thermal-sensor-cells = <1>;
};
bcl_soc:bcl-soc {
compatible = "qcom,msm-bcl-soc";
#thermal-sensor-cells = <0>;
};
pm8350b_haptics: qcom,hv-haptics@f000 {
compatible = "qcom,hv-haptics";
reg = <0xf000>, <0xf100>, <0xf200>;
interrupts = <0x3 0xf0 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "fifo-empty";
qcom,vmax-mv = <3600>;
qcom,brake-mode = <BRAKE_CLOSE_LOOP>;
qcom,brake-pattern = /bits/ 8 <0xff 0x3f 0x1f>;
qcom,lra-period-us = <6667>;
qcom,drv-sig-shape = <WF_SINE>;
qcom,brake-sig-shape = <WF_SINE>;
status = "disabled";
hap_swr_slave_reg: qcom,hap-swr-slave-reg {
regulator-name = "hap-swr-slave-reg";
};
effect_0 {
/* CLICK */
qcom,effect-id = <0>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>,
<0x03f S_PERIOD_T_LRA 0>,
<0x05f S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>,
<0x17f S_PERIOD_T_LRA 0>,
<0x15f S_PERIOD_T_LRA 0>,
<0x13f S_PERIOD_T_LRA 0>,
<0x11f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-pattern-preload;
qcom,wf-auto-res-disable;
};
effect_1 {
/* DOUBLE_CLICK */
qcom,effect-id = <1>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>,
<0x03f S_PERIOD_T_LRA 0>,
<0x05f S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>,
<0x17f S_PERIOD_T_LRA 0>,
<0x15f S_PERIOD_T_LRA 0>,
<0x13f S_PERIOD_T_LRA 0>,
<0x11f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
effect_2 {
/* TICK */
qcom,effect-id = <2>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>,
<0x03f S_PERIOD_T_LRA 0>,
<0x05f S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>,
<0x17f S_PERIOD_T_LRA 0>,
<0x15f S_PERIOD_T_LRA 0>,
<0x13f S_PERIOD_T_LRA 0>,
<0x11f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
effect_3 {
/* THUD */
qcom,effect-id = <3>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>,
<0x03f S_PERIOD_T_LRA 0>,
<0x05f S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>,
<0x17f S_PERIOD_T_LRA 0>,
<0x15f S_PERIOD_T_LRA 0>,
<0x13f S_PERIOD_T_LRA 0>,
<0x11f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
effect_4 {
/* POP */
qcom,effect-id = <4>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>,
<0x03f S_PERIOD_T_LRA 0>,
<0x05f S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>,
<0x17f S_PERIOD_T_LRA 0>,
<0x15f S_PERIOD_T_LRA 0>,
<0x13f S_PERIOD_T_LRA 0>,
<0x11f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
effect_5 {
/* HEAVY CLICK */
qcom,effect-id = <5>;
qcom,wf-vmax-mv = <3600>;
qcom,wf-pattern-data = <0x01f S_PERIOD_T_LRA 0>,
<0x03f S_PERIOD_T_LRA 0>,
<0x05f S_PERIOD_T_LRA 0>,
<0x07f S_PERIOD_T_LRA 0>,
<0x17f S_PERIOD_T_LRA 0>,
<0x15f S_PERIOD_T_LRA 0>,
<0x13f S_PERIOD_T_LRA 0>,
<0x11f S_PERIOD_T_LRA 0>;
qcom,wf-pattern-period-us = <6667>;
qcom,wf-brake-pattern = /bits/ 8 <0x0 0x0 0x0>;
qcom,wf-auto-res-disable;
};
};
pm8350b_amoled: qcom,amoled {
compatible = "qcom,qpnp-amoled-regulator";
#address-cells = <1>;
#size-cells = <0>;
oledb_vreg: oledb@fa00 {
reg = <0xfa00>;
reg-names = "oledb_base";
regulator-name = "oledb";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <8000000>;
qcom,swire-control;
};
ab_vreg: ab@f900 {
reg = <0xf900>;
reg-names = "ab_base";
regulator-name = "ab";
regulator-min-microvolt = <4600000>;
regulator-max-microvolt = <5200000>;
qcom,swire-control;
};
ibb_vreg: ibb@f800 {
reg = <0xf800>;
reg-names = "ibb_base";
regulator-name = "ibb";
regulator-min-microvolt = <1400000>;
regulator-max-microvolt = <6600000>;
qcom,swire-control;
regulator-allow-set-load;
};
};
qcom,amoled-ecm@f900 {
compatible = "qcom,amoled-ecm";
reg = <0xf900>;
nvmem-names = "amoled-ecm-sdam0", "amoled-ecm-sdam1",
"amoled-ecm-sdam2";
nvmem = <&pmk8350_sdam_13>, <&pmk8350_sdam_14>,
<&pmk8350_sdam_41>;
interrupt-names = "ecm-sdam0", "ecm-sdam1",
"ecm-sdam2";
interrupts = <0x0 0x7c 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x7d 0x1 IRQ_TYPE_EDGE_RISING>,
<0x0 0x98 0x1 IRQ_TYPE_EDGE_RISING>;
};
};
};
&thermal_zones {
pm8350b_temp_alarm: pm8350b_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8350b_tz>;
trips {
pm8350b_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8350b_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
pm8350b_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pm8350b-ibat-lvl0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8350b_bcl 0>;
trips {
ibat_lvl0:ibat-lvl0 {
temperature = <6000>;
hysteresis = <200>;
type = "passive";
};
};
};
pm8350b-ibat-lvl1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8350b_bcl 1>;
trips {
ibat_lvl1:ibat-lvl1 {
temperature = <7500>;
hysteresis = <200>;
type = "passive";
};
};
};
pm8350b-bcl-lvl0 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8350b_bcl 5>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl0: b-bcl-lvl0 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pm8350b-bcl-lvl1 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8350b_bcl 6>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl1: b-bcl-lvl1 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pm8350b-bcl-lvl2 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pm8350b_bcl 7>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
b_bcl_lvl2: b-bcl-lvl2 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
socd {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&bcl_soc>;
trips {
thermal-engine-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
thermal-hal-trip {
temperature = <100>;
hysteresis = <0>;
type = "passive";
};
socd_trip:socd-trip {
temperature = <90>;
hysteresis = <0>;
type = "passive";
};
};
};
};

302
qcom/pm8350c.dtsi Normal file
View File

@@ -0,0 +1,302 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pm8350c@2 {
compatible = "qcom,spmi-pmic";
reg = <2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8350c_tz: qcom,temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8350c_gpios: pinctrl@8800 {
compatible = "qcom,pm8350c-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pm8350c_pwm_1: pwms@e800 {
compatible = "qcom,pwm-lpg";
reg = <0xe800>;
reg-names = "lpg-base";
#pwm-cells = <2>;
qcom,num-lpg-channels = <3>;
nvmem = <&pmk8350_sdam_21 &pmk8350_sdam_22>;
nvmem-names = "lpg_chan_sdam", "lut_sdam";
qcom,lut-sdam-base = <0x45>;
qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100
90 80 70 60 50 40 30 20 10 0>;
qcom,tick-duration-us = <8000>;
lpg@1 {
qcom,lpg-chan-id = <1>;
qcom,ramp-step-ms = <100>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x48>;
};
lpg@2 {
qcom,lpg-chan-id = <2>;
qcom,ramp-step-ms = <100>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x56>;
};
lpg@3 {
qcom,lpg-chan-id = <3>;
qcom,ramp-step-ms = <100>;
qcom,ramp-low-index = <0>;
qcom,ramp-high-index = <19>;
qcom,ramp-pattern-repeat;
qcom,lpg-sdam-base = <0x64>;
};
};
pm8350c_pwm_2: pwms@eb00 {
compatible = "qcom,pwm-lpg";
reg = <0xeb00>;
reg-names = "lpg-base";
#pwm-cells = <2>;
qcom,num-lpg-channels = <1>;
};
pm8350c_rgb: qcom,leds@ef00 {
compatible = "qcom,tri-led";
reg = <0xef00>;
red {
label = "red";
pwms = <&pm8350c_pwm_1 0 1000000>;
led-sources = <0>;
linux,default-trigger = "timer";
};
green {
label = "green";
pwms = <&pm8350c_pwm_1 1 1000000>;
led-sources = <1>;
linux,default-trigger = "timer";
};
blue {
label = "blue";
pwms = <&pm8350c_pwm_1 2 1000000>;
led-sources = <2>;
linux,default-trigger = "timer";
};
};
pm8350c_bcl: bcl@4700 {
compatible = "qcom,bcl-v5";
reg = <0x4700 0x100>;
interrupts = <0x2 0x47 0x0 IRQ_TYPE_NONE>,
<0x2 0x47 0x1 IRQ_TYPE_NONE>,
<0x2 0x47 0x2 IRQ_TYPE_NONE>;
interrupt-names = "bcl-lvl0",
"bcl-lvl1",
"bcl-lvl2";
qcom,pmic7-threshold;
#thermal-sensor-cells = <1>;
};
pm8350c_flash: qcom,flash_led@ee00 {
compatible = "qcom,pm8350c-flash-led";
reg = <0xee00>;
interrupts = <0x2 0xee 0x0 IRQ_TYPE_EDGE_RISING>,
<0x2 0xee 0x3 IRQ_TYPE_EDGE_RISING>,
<0x2 0xee 0x4 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "led-fault-irq",
"all-ramp-down-done-irq",
"all-ramp-up-done-irq";
qcom,thermal-derate-current = <200 500>;
qcom,hw-strobe-gpios = <&pm8350c_gpios 1 0>;
status = "disabled";
pm8350c_flash0: qcom,flash_0 {
label = "flash";
qcom,led-name = "led:flash_0";
qcom,max-current-ma = <1500>;
qcom,default-led-trigger = "flash0_trigger";
qcom,id = <0>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
};
pm8350c_flash1: qcom,flash_1 {
label = "flash";
qcom,led-name = "led:flash_1";
qcom,max-current-ma = <1500>;
qcom,default-led-trigger = "flash1_trigger";
qcom,id = <1>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
};
pm8350c_flash2: qcom,flash_2 {
label = "flash";
qcom,led-name = "led:flash_2";
qcom,max-current-ma = <1500>;
qcom,default-led-trigger = "flash2_trigger";
qcom,id = <2>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
};
pm8350c_flash3: qcom,flash_3 {
label = "flash";
qcom,led-name = "led:flash_3";
qcom,max-current-ma = <1500>;
qcom,default-led-trigger = "flash3_trigger";
qcom,id = <3>;
qcom,duration-ms = <1280>;
qcom,ires-ua = <12500>;
};
pm8350c_torch0: qcom,torch_0 {
label = "torch";
qcom,led-name = "led:torch_0";
qcom,max-current-ma = <500>;
qcom,default-led-trigger = "torch0_trigger";
qcom,id = <0>;
qcom,ires-ua = <12500>;
};
pm8350c_torch1: qcom,torch_1 {
label = "torch";
qcom,led-name = "led:torch_1";
qcom,max-current-ma = <500>;
qcom,default-led-trigger = "torch1_trigger";
qcom,id = <1>;
qcom,ires-ua = <12500>;
};
pm8350c_torch2: qcom,torch_2 {
label = "torch";
qcom,led-name = "led:torch_2";
qcom,max-current-ma = <500>;
qcom,default-led-trigger = "torch2_trigger";
qcom,id = <2>;
qcom,ires-ua = <12500>;
};
pm8350c_torch3: qcom,torch_3 {
label = "torch";
qcom,led-name = "led:torch_3";
qcom,max-current-ma = <500>;
qcom,default-led-trigger = "torch3_trigger";
qcom,id = <3>;
qcom,ires-ua = <12500>;
};
pm8350c_switch0: qcom,led_switch_0 {
label = "switch";
qcom,led-name = "led:switch_0";
qcom,default-led-trigger = "switch0_trigger";
};
pm8350c_switch1: qcom,led_switch_1 {
label = "switch";
qcom,led-name = "led:switch_1";
qcom,default-led-trigger = "switch1_trigger";
};
pm8350c_switch2: qcom,led_switch_2 {
label = "switch";
qcom,led-name = "led:switch_2";
qcom,default-led-trigger = "switch2_trigger";
};
};
};
};
&thermal_zones {
pm8350c_temp_alarm: pm8350c_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8350c_tz>;
trips {
pm8350c_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8350c_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
pm8350c_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pm8350c-bcl-lvl0 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8350c_bcl 5>;
trips {
c_bcl_lvl0: c-bcl-lvl0 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pm8350c-bcl-lvl1 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8350c_bcl 6>;
trips {
c_bcl_lvl1: c-bcl-lvl1 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
pm8350c-bcl-lvl2 {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8350c_bcl 7>;
trips {
c_bcl_lvl2: c-bcl-lvl2 {
temperature = <1>;
hysteresis = <1>;
type = "passive";
};
};
};
};

61
qcom/pm8450.dtsi Normal file
View File

@@ -0,0 +1,61 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pm8450@7 {
compatible = "qcom,spmi-pmic";
reg = <7 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8450_tz: qcom,temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pm8450_gpios: pinctrl@8800 {
compatible = "qcom,pm8450-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
&thermal_zones {
pm8450_temp_alarm: pm8450_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8450_tz>;
trips {
pm8450_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pm8450_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
pm8450_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};

253
qcom/pmk8350.dtsi Normal file
View File

@@ -0,0 +1,253 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/qcom,qpnp-power-on.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmr735b.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
pmk8350: qcom,pmk8350@0 {
compatible = "qcom,spmi-pmic";
reg = <0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pon_pbs@800 {
compatible = "qcom,qpnp-power-on";
reg = <0x800>;
qcom,system-reset;
qcom,store-hard-reset-reason;
};
pon_hlos@1300 {
compatible = "qcom,qpnp-power-on";
reg = <0x1300>;
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>,
<0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "kpdpwr", "resin";
qcom,pon_1 {
qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
linux,code = <KEY_POWER>;
};
qcom,pon_2 {
qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
pmk8350_vadc: vadc@3100 {
compatible = "qcom,spmi-adc7";
reg = <0x3100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "eoc-int-en-set";
#io-channel-cells = <1>;
io-channel-ranges;
/* PMK8350 Channel nodes */
pmk8350_ref_gnd {
reg = <PMK8350_ADC7_REF_GND>;
label = "pmk8350_ref_gnd";
qcom,pre-scaling = <1 1>;
};
pmk8350_vref_1p25 {
reg = <PMK8350_ADC7_1P25VREF>;
label = "pmk8350_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pmk8350_die_temp {
reg = <PMK8350_ADC7_DIE_TEMP>;
label = "pmk8350_die_temp";
qcom,pre-scaling = <1 1>;
};
pmk8350_xo_therm {
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
label = "pmk8350_xo_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
/* PM8350 Channel nodes */
pm8350_ref_gnd {
reg = <PM8350_ADC7_REF_GND>;
label = "pm8350_ref_gnd";
qcom,pre-scaling = <1 1>;
};
pm8350_vref_1p25 {
reg = <PM8350_ADC7_1P25VREF>;
label = "pm8350_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pm8350_die_temp {
reg = <PM8350_ADC7_DIE_TEMP>;
label = "pm8350_die_temp";
qcom,pre-scaling = <1 1>;
};
pm8350_vph_pwr {
reg = <PM8350_ADC7_VPH_PWR>;
label = "pm8350_vph_pwr";
qcom,pre-scaling = <1 3>;
};
/* PM8350b Channel nodes */
pm8350b_ref_gnd {
reg = <PM8350B_ADC7_REF_GND>;
label = "pm8350b_ref_gnd";
qcom,pre-scaling = <1 1>;
};
pm8350b_vref_1p25 {
reg = <PM8350B_ADC7_1P25VREF>;
label = "pm8350b_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pm8350b_die_temp {
reg = <PM8350B_ADC7_DIE_TEMP>;
label = "pm8350b_die_temp";
qcom,pre-scaling = <1 1>;
};
pm8350b_vph_pwr {
reg = <PM8350B_ADC7_VPH_PWR>;
label = "pm8350b_vph_pwr";
qcom,pre-scaling = <1 3>;
};
pm8350b_vbat_sns {
reg = <PM8350B_ADC7_VBAT_SNS>;
label = "pm8350b_vbat_sns";
qcom,pre-scaling = <1 3>;
};
/* PMR735a Channel nodes */
pmr735a_ref_gnd {
reg = <PMR735A_ADC7_REF_GND>;
label = "pmr735a_ref_gnd";
qcom,pre-scaling = <1 1>;
};
pmr735a_vref_1p25 {
reg = <PMR735A_ADC7_1P25VREF>;
label = "pmr735a_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pmr735a_die_temp {
reg = <PMR735A_ADC7_DIE_TEMP>;
label = "pmr735a_die_temp";
qcom,pre-scaling = <1 1>;
};
/* PMR735b Channel nodes */
pmr735b_ref_gnd {
reg = <PMR735B_ADC7_REF_GND>;
label = "pmr735b_ref_gnd";
qcom,pre-scaling = <1 1>;
};
pmr735b_vref_1p25 {
reg = <PMR735B_ADC7_1P25VREF>;
label = "pmr735b_vref_1p25";
qcom,pre-scaling = <1 1>;
};
pmr735b_die_temp {
reg = <PMR735B_ADC7_DIE_TEMP>;
label = "pmr735b_die_temp";
qcom,pre-scaling = <1 1>;
};
};
pmk8350_adc_tm: adc_tm@3400 {
compatible = "qcom,adc-tm7";
reg = <0x3400>;
interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "threshold";
#address-cells = <1>;
#size-cells = <0>;
#thermal-sensor-cells = <1>;
};
pmk8350_sdam_2: sdam@7100 {
compatible = "qcom,spmi-sdam";
reg = <0x7100>;
#address-cells = <1>;
#size-cells = <1>;
restart_reason: restart@48 {
reg = <0x48 0x1>;
bits = <1 7>;
};
};
pmk8350_sdam_5: sdam@7400 {
compatible = "qcom,spmi-sdam";
reg = <0x7400>;
};
pmk8350_sdam_13: sdam@7c00 {
compatible = "qcom,spmi-sdam";
reg = <0x7c00>;
};
pmk8350_sdam_14: sdam@7d00 {
compatible = "qcom,spmi-sdam";
reg = <0x7d00>;
};
pmk8350_sdam_21: sdam@8400 {
compatible = "qcom,spmi-sdam";
reg = <0x8400>;
};
pmk8350_sdam_22: sdam@8500 {
compatible = "qcom,spmi-sdam";
reg = <0x8500>;
};
pmk8350_sdam_41: sdam@9800 {
compatible = "qcom,spmi-sdam";
reg = <0x9800>;
};
pmk8350_sdam_46: sdam@9d00 {
compatible = "qcom,spmi-sdam";
reg = <0x9d00>;
};
pmk8350_gpios: pinctrl@b000 {
compatible = "qcom,pmk8350-gpio";
reg = <0xb000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
pmk8350_rtc: rtc@6100 {
compatible = "qcom,pmk8350-rtc";
reg = <0x6100>, <0x6200>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
};
};
};

61
qcom/pmr735a.dtsi Normal file
View File

@@ -0,0 +1,61 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pmr735a@4 {
compatible = "qcom,spmi-pmic";
reg = <4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmr735a_tz: qcom,temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmr735a_gpios: pinctrl@8800 {
compatible = "qcom,pmr735a-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
&thermal_zones {
pmr735a_temp_alarm: pmr735a_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pmr735a_tz>;
trips {
pmr735a_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pmr735a_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
pmr735a_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};

61
qcom/pmr735b.dtsi Normal file
View File

@@ -0,0 +1,61 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pmr735b@5 {
compatible = "qcom,spmi-pmic";
reg = <5 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmr735b_tz: qcom,temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmr735b_gpios: pinctrl@8800 {
compatible = "qcom,pmr735b-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
&thermal_zones {
pmr735b_temp_alarm: pmr735b_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pmr735b_tz>;
trips {
pmr735b_trip0: trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
pmr735b_trip1: trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
pmr735b_trip2: trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};

51
qcom/sdxlemur-external-soc.dtsi Normal file
View File

@@ -0,0 +1,51 @@
&soc {
mdm0: qcom,remoteproc-esoc0 {
cell-index = <0>;
#address-cells = <0>;
interrupt-parent = <&mdm0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-names =
"err_fatal_irq",
"status_irq";
interrupt-map = <0 &tlmm 36 0x3
1 &tlmm 40 0x3>;
/* modem attributes */
qcom,ramdump-delay-ms = <3000>;
qcom,ramdump-timeout-ms = <120000>;
qcom,vddmin-modes = "normal";
qcom,vddmin-drive-strength = <8>;
qcom,sfr-query;
qcom,sysmon-id = <20>;
qcom,ssctl-instance-id = <0x10>;
qcom,support-shutdown;
qcom,pil-force-shutdown;
pinctrl-names = "default", "mdm_active", "mdm_suspend";
pinctrl-0 = <&ap2mdm_pon_reset_default>;
pinctrl-1 = <&ap2mdm_active &mdm2ap_active>;
pinctrl-2 = <&ap2mdm_sleep &mdm2ap_sleep>;
qcom,mdm2ap-errfatal-gpio = <&tlmm 36 0x00>;
qcom,ap2mdm-errfatal-gpio = <&tlmm 37 0x00>;
qcom,mdm2ap-status-gpio = <&tlmm 40 0x00>;
qcom,ap2mdm-status-gpio = <&tlmm 41 0x00>;
qcom,ap2mdm-soft-reset-gpio = <&pm8450_gpios 1 0>;
reg-names = "l10c";
l10c-supply = <&L10C>;
l10c-uV-uA = <1200000 100000>;
qcom,esoc-skip-restart-for-mdm-crash;
status = "ok";
};
};
&pm8450_gpios {
ap2mdm_pon_reset {
ap2mdm_pon_reset_default: ap2mdm_pon_reset_default {
/* MDM PON control*/
pins = "gpio1";
function = "normal";
power-source = <1>; /* 1.8V */
};
};
};

12
qcom/waipio-atp-pm8008-overlay.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
#include "waipio-atp.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio ATP with PM8008";
compatible = "qcom,waipio-atp", "qcom,waipio", "qcom,atp";
qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
qcom,board-id = <0x10021 0>;
};

11
qcom/waipio-atp-pm8008.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio.dtsi"
#include "waipio-atp.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio ATP with PM8008";
compatible = "qcom,waipio-atp", "qcom,waipio", "qcom,atp";
qcom,board-id = <33 0>;
};

12
qcom/waipio-atp-pm8010-overlay.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
#include "waipio-atp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio ATP with PM8010";
compatible = "qcom,waipio-atp", "qcom,waipio", "qcom,atp";
qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
qcom,board-id = <0x10021 0>;
};

11
qcom/waipio-atp-pm8010.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio.dtsi"
#include "waipio-atp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio ATP with PM8010";
compatible = "qcom,waipio-atp", "qcom,waipio", "qcom,atp";
qcom,board-id = <0x10021 0>;
};

1
qcom/waipio-atp.dtsi Normal file
View File

@@ -0,0 +1 @@
#include "waipio-mtp.dtsi"

12
qcom/waipio-cdp-pm8008-overlay.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
#include "waipio-cdp.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio CDP with PM8008";
compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
qcom,board-id = <0x10001 0>;
};

11
qcom/waipio-cdp-pm8008.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio.dtsi"
#include "waipio-cdp.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio CDP with PM8008";
compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
qcom,board-id = <1 0>;
};

12
qcom/waipio-cdp-pm8010-overlay.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
#include "waipio-cdp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio CDP with PM8010";
compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
qcom,board-id = <0x10001 0>;
};

11
qcom/waipio-cdp-pm8010.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio.dtsi"
#include "waipio-cdp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio CDP with PM8010";
compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
qcom,board-id = <0x10001 0>;
};

222
qcom/waipio-cdp.dtsi Normal file
View File

@@ -0,0 +1,222 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "waipio-pmic-overlay.dtsi"
#include "waipio-thermal-overlay.dtsi"
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-waipio";
vdda-phy-supply = <&pm8350_l5>;
vdda-pll-supply = <&pm8350_l6>;
vdda-phy-max-microamp = <173000>;
vdda-pll-max-microamp = <24900>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&pm8350_l7>;
vcc-max-microamp = <1100000>;
vccq-supply = <&pm8350_l9>;
vccq-max-microamp = <1200000>;
qcom,vddp-ref-clk-supply = <&pm8350_l9>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq-parent-supply = <&pm8350_s12>;
qcom,vccq-parent-max-microamp = <210000>;
status = "ok";
};
&sdhc_2 {
status = "ok";
vdd-supply = <&pm8350c_l9>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&pm8350c_l6>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
};
&soc {
gpio_keys {
compatible = "gpio-keys";
label = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_vol_up_default>;
vol_up {
label = "volume_up";
gpios = <&pm8350_gpios 6 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
debounce-interval = <15>;
linux,can-disable;
};
};
};
&pm8350b_haptics {
status = "ok";
};
&pm8350c_switch0 {
qcom,led-mask = <9>; /* Channels 1 & 4 */
qcom,symmetry-en;
};
&pm8350c_switch1 {
qcom,led-mask = <6>; /* Channels 2 & 3 */
qcom,symmetry-en;
};
&pm8350c_switch2 {
qcom,led-mask = <15>; /* All Channels */
qcom,symmetry-en;
};
&pm8350c_flash {
status = "ok";
};
&qupv3_se9_i2c {
status = "ok";
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 46 0x00>;
qcom,sn-ven = <&tlmm 34 0x00>;
qcom,sn-firm = <&tlmm 45 0x00>;
qcom,sn-clkreq = <&tlmm 35 0x00>;
qcom,sn-vdd-1p8-supply = <&S10B>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <46 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};
&qupv3_se4_i2c {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,i2c-touch-active = "focaltech,fts_ts";
focaltech@38 {
compatible = "focaltech,fts_ts";
reg = <0x38>;
interrupt-parent = <&tlmm>;
interrupts = <21 0x2008>;
focaltech,reset-gpio = <&tlmm 20 0x00>;
focaltech,irq-gpio = <&tlmm 21 0x2008>;
focaltech,max-touch-number = <5>;
focaltech,display-coords = <0 0 1080 2340>;
focaltech,touch-type = "primary";
vdd-supply = <&L3C>;
vcc_i2c-supply = <&L8C>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "pvm";
focaltech,trusted-touch-spi-irq = <754>;
focaltech,trusted-touch-io-bases = <0xF110000 0xF111000 0xF112000 0xF113000
0xF114000 0xF115000 0x990000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000
0x1000 0x1000 0x1000 0x4000>;
};
atmel_mxt_ts@4a {
compatible = "atmel,maxtouch";
reg = <0x4a>;
interrupt-parent = <&tlmm>;
interrupts = <21 0x2008>;
avdd-supply = <&L3C>;
vdd-supply = <&L8C>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
atmel,xy_switch;
atmel,inverty;
atmel,invertx;
reset-gpios = <&tlmm 20 0x00>;
irq-gpios = <&tlmm 21 0x2008>;
atmel,panel-coords = <0 0 479 799>;
atmel,display-coords = <0 0 339 729>;
};
synaptics_dsx@22 {
compatible = "synaptics,dsx-i2c";
reg = <0x22>;
interrupt-parent = <&tlmm>;
interrupts = <21 0x2008>;
vdd-supply = <&L8C>;
avdd-supply = <&L3C>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
synaptics,pwr-reg-name = "avdd";
synaptics,bus-reg-name = "vdd";
synaptics,ub-i2c-addr = <0x22>;
synaptics,max-y-for-2d = <1859>;
synaptics,irq-gpio = <&tlmm 21 0x2008>;
synaptics,reset-gpio = <&tlmm 20 0x00>;
synaptics,irq-on-state = <0>;
synaptics,power-delay-ms = <200>;
synaptics,reset-delay-ms = <200>;
synaptics,reset-on-state = <0>;
synaptics,reset-active-ms = <20>;
};
};
&usb0 {
usb-role-switch;
dwc3@a600000 {
usb-role-switch;
dr_mode = "otg";
};
port {
usb_port0: endpoint {
remote-endpoint = <&usb_port0_connector>;
};
};
};
&ucsi {
connector {
port {
usb_port0_connector: endpoint {
remote-endpoint = <&usb_port0>;
};
};
};
};

4015
qcom/waipio-coresight.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

2783
qcom/waipio-debug.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

71
qcom/waipio-dma-heaps.dtsi Normal file
View File

@@ -0,0 +1,71 @@
#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
&soc {
qcom,dma-heaps {
compatible = "qcom,dma-heaps";
qcom,adsp {
qcom,dma-heap-name = "qcom,adsp";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&sdsp_mem>;
};
qcom,secure_cdsp {
qcom,dma-heap-name = "qcom,secure-cdsp";
qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>;
memory-region = <&cdsp_secure_heap>;
qcom,token = <0x20000000>;
};
qcom,sp_hlos {
qcom,dma-heap-name = "qcom,sp-hlos";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&sp_mem>;
};
qcom,secure_sp_modem {
qcom,dma-heap-name = "qcom,secure-sp-modem";
qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>;
memory-region = <&spu_modem_shared_mem>;
qcom,token = <0x10800000>;
};
qcom,secure_sp_tz {
qcom,dma-heap-name = "qcom,secure-sp-tz";
qcom,dma-heap-type = <HEAP_TYPE_SECURE_CARVEOUT>;
memory-region = <&spu_tz_shared_mem>;
qcom,token = <0x01000000>;
};
qcom,user_contig {
qcom,dma-heap-name = "qcom,user-contig";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&user_contig_mem>;
};
qcom,qseecom {
qcom,dma-heap-name = "qcom,qseecom";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&qseecom_mem>;
};
qcom,qseecom_ta {
qcom,dma-heap-name = "qcom,qseecom-ta";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&qseecom_ta_mem>;
};
qcom,display {
qcom,dma-heap-name = "qcom,display";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
qcom,max-align = <9>;
memory-region = <&non_secure_display_memory>;
};
qcom,audio_ml {
qcom,dma-heap-name = "qcom,audio-ml";
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
memory-region = <&audio_cma_mem>;
};
};
};

110
qcom/waipio-eva.dtsi Normal file
View File

@@ -0,0 +1,110 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/interconnect/qcom,waipio.h>
#include <dt-bindings/clock/qcom,videocc-waipio.h>
&soc {
msm_cvp: qcom,cvp@ab00000 {
compatible = "qcom,msm-cvp", "qcom,waipio-cvp";
status = "ok";
reg = <0xab00000 0x100000>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
/* LLCC Cache */
cache-slice-names = "cvp";
/* Supply */
cvp-supply = <&video_cc_mvs1c_gdsc>;
cvp-core-supply = <&video_cc_mvs1_gdsc>;
/* Clocks */
clock-names = "gcc_video_axi1", "cvp_clk", "core_clk",
"video_cc_mvs1_clk_src";
clock-ids = <GCC_VIDEO_AXI1_CLK VIDEO_CC_MVS1C_CLK
VIDEO_CC_MVS1_CLK VIDEO_CC_MVS1_CLK_SRC>;
clocks = <&clock_gcc GCC_VIDEO_AXI1_CLK>,
<&clock_videocc VIDEO_CC_MVS1C_CLK>,
<&clock_videocc VIDEO_CC_MVS1_CLK>,
<&clock_videocc VIDEO_CC_MVS1_CLK_SRC>;
qcom,proxy-clock-names = "gcc_video_axi1",
"cvp_clk", "core_clk", "video_cc_mvs1_clk_src";
qcom,clock-configs = <0x0 0x0 0x0 0x1>;
qcom,allowed-clock-rates = <350000000 450000000 500000000 550000000>;
resets = <&clock_gcc GCC_VIDEO_AXI1_CLK_ARES>,
<&clock_videocc VIDEO_CC_MVS1C_CLK_ARES>;
reset-names = "cvp_axi_reset", "cvp_core_reset";
reset-power-status = <0x2 0x2>;
qcom,reg-presets = <0xB0088 0x0>;
qcom,ipcc-reg = <0x400000 0x100000>;
qcom,gcc-reg = <0x110000 0x40000>;
pas-id = <26>;
memory-region = <&cvp_mem>;
/* CVP Firmware ELF image name */
cvp,firmware-name = "evass";
/* Buses */
cvp_cnoc {
compatible = "qcom,msm-cvp,bus";
label = "cvp-cnoc";
qcom,bus-master = <MASTER_APPSS_PROC>;
qcom,bus-slave = <SLAVE_VENUS_CFG>;
qcom,bus-governor = "performance";
qcom,bus-range-kbps = <1000 1000>;
};
cvp_bus_ddr {
compatible = "qcom,msm-cvp,bus";
label = "cvp-ddr";
qcom,bus-master = <MASTER_VIDEO_PROC>;
qcom,bus-slave = <SLAVE_EBI1>;
qcom,bus-governor = "performance";
qcom,bus-range-kbps = <1000 6533000>;
};
/* MMUs */
cvp_non_secure_cb {
compatible = "qcom,msm-cvp,context-bank";
label = "cvp_hlos";
iommus =
<&apps_smmu 0x21a0 0x400>;
buffer-types = <0xfff>;
dma-coherent;
qcom,iommu-faults = "non-fatal";
qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>;
};
cvp_secure_nonpixel_cb {
compatible = "qcom,msm-cvp,context-bank";
label = "cvp_sec_nonpixel";
iommus =
<&apps_smmu 0x21a4 0x400>;
buffer-types = <0x741>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>;
qcom,iommu-vmid = <0xB>;
};
cvp_secure_pixel_cb {
compatible = "qcom,msm-cvp,context-bank";
label = "cvp_sec_pixel";
iommus =
<&apps_smmu 0x21a3 0x400>;
buffer-types = <0x106>;
qcom,iommu-faults = "non-fatal";
qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>;
qcom,iommu-vmid = <0xA>;
};
/* Memory Heaps */
qcom,msm-cvp,mem_cdsp {
compatible = "qcom,msm-cvp,mem-cdsp";
memory-region = <&cdsp_eva_mem>;
};
};
};

283
qcom/waipio-gpu.dtsi Normal file
View File

@@ -0,0 +1,283 @@
#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
&soc {
msm_gpu: qcom,kgsl-3d0@3d00000 {
compatible = "qcom,adreno-gpu-c500", "qcom,kgsl-3d0";
status = "ok";
reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
<0x03d50000 0x10000>, <0x3d8b000 0x2000>,
<0x03d9e000 0x1000>, <0x10900000 0x80000>;
reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
"isense_cntl", "cx_misc", "qdss_gfx";
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "kgsl_3d0_irq";
clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
<&clock_gpucc GPU_CC_AHB_CLK>,
<&aoss_qmp QDSS_CLK>;
clock-names = "gcc_gpu_memnoc_gfx",
"gcc_gpu_snoc_dvm_gfx",
"gpu_cc_ahb", "apb_pclk";
qcom,gpu-model = "Adreno730v1";
qcom,initial-pwrlevel = <8>;
qcom,no-nap;
qcom,min-access-length = <32>;
qcom,ubwc-mode = <4>;
qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
qcom,tzone-names = "gpuss-0", "gpuss-1";
interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>;
interconnect-names = "gpu_icc_path";
qcom,bus-table-cnoc =
<0>, /* Off */
<100>; /* On */
qcom,bus-table-ddr =
<MHZ_TO_KBPS(0, 4)>, /* index=0 */
<MHZ_TO_KBPS(200, 4)>, /* index=1 */
<MHZ_TO_KBPS(451, 4)>, /* index=2 */
<MHZ_TO_KBPS(547, 4)>, /* index=3 */
<MHZ_TO_KBPS(681, 4)>, /* index=4 */
<MHZ_TO_KBPS(768, 4)>, /* index=5 */
<MHZ_TO_KBPS(1555, 4)>, /* index=6 */
<MHZ_TO_KBPS(1708, 4)>, /* index=7 */
<MHZ_TO_KBPS(2092, 4)>, /* index=8 */
<MHZ_TO_KBPS(2736, 4)>, /* index=9 */
<MHZ_TO_KBPS(3196, 4)>; /* index=10 */
zap-shader {
memory-region = <&gpu_micro_code_mem>;
};
/* Power levels */
qcom,gpu-pwrlevels {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels";
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <818000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq = <10>;
qcom,bus-min = <10>;
qcom,bus-max = <10>;
qcom,acd-level = <0x882c5ffd>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <791000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
qcom,bus-freq = <10>;
qcom,bus-min = <9>;
qcom,bus-max = <10>;
qcom,acd-level = <0x882c5ffd>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <10>;
qcom,bus-min = <9>;
qcom,bus-max = <10>;
qcom,acd-level = <0x882d5ffd>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <640000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <10>;
qcom,bus-min = <6>;
qcom,bus-max = <10>;
qcom,acd-level = <0xa82d5ffd>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <599000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <545000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <8>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <492000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <6>;
qcom,bus-min = <6>;
qcom,bus-max = <8>;
qcom,acd-level = <0x882e5ffd>;
};
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <421000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <6>;
qcom,bus-min = <3>;
qcom,bus-max = <8>;
qcom,acd-level = <0xa82e5ffd>;
};
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <350000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <2>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
qcom,acd-level = <0x882f5ffd>;
};
};
qcom,gpu-mempools {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-mempools";
/* 4K Page Pool configuration */
qcom,gpu-mempool@0 {
reg = <0>;
qcom,mempool-page-size = <4096>;
qcom,mempool-reserved = <2048>;
};
/* 8K Page Pool configuration */
qcom,gpu-mempool@1 {
reg = <1>;
qcom,mempool-page-size = <8192>;
qcom,mempool-reserved = <1024>;
};
/* 64K Page Pool configuration */
qcom,gpu-mempool@2 {
reg = <2>;
qcom,mempool-page-size = <65536>;
qcom,mempool-reserved = <256>;
};
/* 128K Page Pool configuration */
qcom,gpu-mempool@3 {
reg = <3>;
qcom,mempool-page-size = <131072>;
qcom,mempool-reserved = <128>;
};
/* 256K Page Pool configuration */
qcom,gpu-mempool@4 {
reg = <4>;
qcom,mempool-page-size = <262144>;
qcom,mempool-reserved = <80>;
};
/* 1M Page Pool configuration */
qcom,gpu-mempool@5 {
reg = <5>;
qcom,mempool-page-size = <1048576>;
qcom,mempool-reserved = <32>;
};
};
};
kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
compatible = "qcom,kgsl-smmu-v2";
reg = <0x03da0000 0x40000>;
vddcx-supply = <&gpu_cc_cx_gdsc>;
gfx3d_user: gfx3d_user {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x0 0x400>;
qcom,iommu-dma = "disabled";
};
gfx3d_lpac: gfx3d_lpac {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x1 0x400>;
qcom,iommu-dma = "disabled";
};
gfx3d_secure: gfx3d_secure {
compatible = "qcom,smmu-kgsl-cb";
iommus = <&kgsl_smmu 0x2 0x400>;
qcom,iommu-dma = "disabled";
};
};
gmu: qcom,gmu@3d69000 {
compatible = "qcom,genc-gmu";
reg = <0x3d68000 0x37000>,
<0xb290000 0x10000>,
<0x03D40000 0x10000>;
reg-names = "gmu", "gmu_pdc", "gmu_ao_blk_dec0";
interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
<0 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu";
regulator-names = "vddcx", "vdd";
vddcx-supply = <&gpu_cc_cx_gdsc>;
vdd-supply = <&gpu_cc_gx_gdsc>;
clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
<&clock_gpucc GPU_CC_CXO_CLK>,
<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&clock_gpucc GPU_CC_AHB_CLK>,
<&clock_gpucc GPU_CC_HUB_CX_INT_CLK>,
<&aoss_qmp>;
clock-names = "gmu_clk", "cxo_clk", "axi_clk",
"memnoc_clk", "ahb_clk", "hub_clk", "apb_pclk";
iommus = <&kgsl_smmu 0x5 0x400>;
qcom,iommu-dma = "disabled";
mboxes = <&qmp_aop 0>;
mbox-names = "aop";
};
};

1
qcom/waipio-hdk.dtsi Normal file
View File

@@ -0,0 +1 @@
#include "waipio-qrd.dtsi"

12
qcom/waipio-kiwi-mtp-pm8008-overlay.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
#include "waipio-mtp.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio with kiwi";
compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
qcom,board-id = <0x02010008 0>;
};

12
qcom/waipio-kiwi-mtp-pm8010-overlay.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
#include "waipio-mtp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio with Kiwi";
compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
qcom,board-id = <0x02010008 0>;
};

14
qcom/waipio-lemur-cdp-pm8008-overlay.dts Normal file
View File

@@ -0,0 +1,14 @@
/dts-v1/;
/plugin/;
#include "waipio-mtp.dtsi"
#include "waipio-pm8008.dtsi"
#include "sdxlemur-external-soc.dtsi"
#include "waipio-lemur.dtsi"
/ {
model = "WAIPIO LEMUR CDP";
compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
qcom,msm-id = <457 0x10000>;
qcom,board-id = <0x01010001 0x1>;
};

14
qcom/waipio-lemur-cdp-pm8010-overlay.dts Normal file
View File

@@ -0,0 +1,14 @@
/dts-v1/;
/plugin/;
#include "waipio-mtp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
#include "sdxlemur-external-soc.dtsi"
#include "waipio-lemur.dtsi"
/ {
model = "WAIPIO LEMUR CDP";
compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
qcom,msm-id = <457 0x10000>;
qcom,board-id = <0x01010001 0x1>;
};

14
qcom/waipio-lemur-mtp-pm8008-overlay.dts Normal file
View File

@@ -0,0 +1,14 @@
/dts-v1/;
/plugin/;
#include "waipio-mtp.dtsi"
#include "waipio-pm8008.dtsi"
#include "sdxlemur-external-soc.dtsi"
#include "waipio-lemur.dtsi"
/ {
model = "WAIPIO LEMUR MTP";
compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
qcom,msm-id = <457 0x10000>;
qcom,board-id = <0x01010008 0x1>;
};

14
qcom/waipio-lemur-mtp-pm8010-overlay.dts Normal file
View File

@@ -0,0 +1,14 @@
/dts-v1/;
/plugin/;
#include "waipio-mtp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
#include "sdxlemur-external-soc.dtsi"
#include "waipio-lemur.dtsi"
/ {
model = "WAIPIO LEMUR MTP";
compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
qcom,msm-id = <457 0x10000>;
qcom,board-id = <0x01010008 0x1>;
};

252
qcom/waipio-lemur.dtsi Normal file
View File

@@ -0,0 +1,252 @@
#include <dt-bindings/interconnect/qcom,waipio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
&mdm0 {
compatible = "qcom,ext-lemur";
qcom,mdm-link-info = "0308_01.01.00";
};
&modem_pas {
status = "disabled";
};
&pcie1 {
qcom,target-link-width = <1>; /* force X1 lane width */
qcom,no-l0s-supported;
qcom,target-link-speed = <4>; /* Set max link speed to Gen4 */
qcom,vreg-0p9-voltage-level = <912000 912000 193000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000
/* Gen4 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_NOM
100000000>;
qcom,pcie-phy-ver = <105>;
qcom,phy-sequence = <0x1240 0x03 0x0
0x101c 0x31 0x0
0x1020 0x01 0x0
0x1024 0xde 0x0
0x1028 0x07 0x0
0x1030 0x97 0x0
0x1034 0x0c 0x0
0x1044 0x14 0x0
0x1048 0x90 0x0
0x1058 0x0f 0x0
0x1074 0x06 0x0
0x1078 0x06 0x0
0x107c 0x16 0x0
0x1080 0x16 0x0
0x1084 0x36 0x0
0x1088 0x36 0x0
0x1094 0x08 0x0
0x10a4 0x46 0x0
0x10a8 0x04 0x0
0x10ac 0x0a 0x0
0x10b0 0x1a 0x0
0x10b4 0x14 0x0
0x10b8 0x34 0x0
0x10bc 0x82 0x0
0x10c4 0xd0 0x0
0x10cc 0x55 0x0
0x10d0 0x55 0x0
0x10d4 0x03 0x0
0x10d8 0x55 0x0
0x10dc 0x55 0x0
0x10e0 0x05 0x0
0x110c 0x02 0x0
0x1154 0x34 0x0
0x1158 0x12 0x0
0x115c 0x00 0x0
0x1168 0x0a 0x0
0x116c 0x04 0x0
0x119c 0x88 0x0
0x1174 0x20 0x0
0x117c 0x06 0x0
0x11a0 0x14 0x0
0x11a8 0x0f 0x0
0x0220 0x16 0x0
0x03c0 0x38 0x0
0x0a20 0x16 0x0
0x0bc0 0x38 0x0
0x0364 0xcc 0x0
0x0368 0x12 0x0
0x036c 0xcc 0x0
0x0374 0x4a 0x0
0x0378 0x29 0x0
0x037c 0xc5 0x0
0x0380 0xad 0x0
0x0384 0xb6 0x0
0x0388 0xc0 0x0
0x038c 0x1f 0x0
0x0390 0xfb 0x0
0x0394 0x0f 0x0
0x0398 0xc7 0x0
0x039c 0xef 0x0
0x03a0 0xbf 0x0
0x03a4 0xa0 0x0
0x03a8 0x81 0x0
0x03ac 0xde 0x0
0x03b0 0x7f 0x0
0x0b64 0xcc 0x0
0x0b68 0x12 0x0
0x0b6c 0xcc 0x0
0x0b74 0x4a 0x0
0x0b78 0x29 0x0
0x0b7c 0xc5 0x0
0x0b80 0xad 0x0
0x0b84 0xb6 0x0
0x0b88 0xc0 0x0
0x0b8c 0x1f 0x0
0x0b90 0xfb 0x0
0x0b94 0x0f 0x0
0x0b98 0xc7 0x0
0x0b9c 0xef 0x0
0x0ba0 0xbf 0x0
0x0ba4 0xa0 0x0
0x0ba8 0x81 0x0
0x0bac 0xde 0x0
0x0bb0 0x7f 0x0
0x03b4 0x20 0x0
0x022c 0x3f 0x0
0x0230 0x37 0x0
0x0bb4 0x20 0x0
0x0a2c 0x3f 0x0
0x0a30 0x37 0x0
0x0078 0x05 0x0
0x007c 0xf6 0x0
0x0878 0x05 0x0
0x087c 0xf6 0x0
0x0290 0x05 0x0
0x0a90 0x05 0x0
0x03f8 0x1f 0x0
0x0400 0x1f 0x0
0x0408 0x1f 0x0
0x0410 0x1f 0x0
0x0418 0x1f 0x0
0x0420 0x1f 0x0
0x03f4 0x1f 0x0
0x03fc 0x1f 0x0
0x0404 0x1f 0x0
0x0bf8 0x1f 0x0
0x0c00 0x1f 0x0
0x0c08 0x1f 0x0
0x0c10 0x1f 0x0
0x0c18 0x1f 0x0
0x0c20 0x1f 0x0
0x0bf4 0x1f 0x0
0x0bfc 0x1f 0x0
0x0c04 0x1f 0x0
0x0208 0x0c 0x0
0x0a08 0x0c 0x0
0x020c 0x0a 0x0
0x0a0c 0x0a 0x0
0x02dc 0x0a 0x0
0x0adc 0x0a 0x0
0x0308 0x0b 0x0
0x0b08 0x0b 0x0
0x027c 0x10 0x0
0x0a7c 0x10 0x0
0x02b4 0x00 0x0
0x0ab4 0x00 0x0
0x02ec 0x0f 0x0
0x0aec 0x0f 0x0
0x02c4 0x00 0x0
0x02c8 0x1f 0x0
0x0ac4 0x00 0x0
0x0ac8 0x1f 0x0
0x0030 0x1a 0x0
0x0034 0x0c 0x0
0x0830 0x1a 0x0
0x0834 0x0c 0x0
0x141c 0xc1 0x0
0x1490 0x00 0x0
0x13e0 0x16 0x0
0x13e4 0x22 0x0
0x1508 0x02 0x0
0x14a0 0x16 0x0
0x1584 0x28 0x0
0x1370 0x2e 0x0
0x155c 0x2e 0x0
0x1388 0x99 0x0
0x1e24 0x01 0x0
0x1e28 0x01 0x0
0x1828 0x50 0x0
0x1c28 0x50 0x0
0x1200 0x00 0x0
0x1244 0x03 0x0>;
};
&soc {
qcom,ipa-mpm {
compatible = "qcom,ipa-mpm";
qcom,iova-mapping = <0x10000000 0x0FFFFFFF>;
};
qcom,qbt_handler {
status = "disabled";
};
};
&ipa_hw {
status = "ok";
qcom,platform-type = <2>; /* APQ platform */
qcom,entire-ipa-block-size = <0x100000>;
qcom,register-collection-on-crash;
qcom,testbus-collection-on-crash;
qcom,non-tn-collection-on-crash;
qcom,ram-collection-on-crash;
qcom,secure-debug-check-action = <0>;
};
&tlmm {
qcom,gpios-reserved = <28 29 30 31>;
};
&pcie1_rp {
#address-cells = <5>;
#size-cells = <0>;
mhi0: qcom,mhi@0 {
reg = <0 0 0 0 0 >;
esoc-names = "mdm";
esoc-0 = <&mdm0>;
interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
interconnect-names = "pcie_to_ddr";
qcom,mhi-bus-bw-cfg =
<0 0>, /* no vote */
<250000 0>, /* avg bw / AB: 2 GBps, peak bw / IB: no vote */
<500000 0>, /* avg bw / AB: 4 GBps, peak bw / IB: no vote */
<1000000 0>, /* avg bw / AB: 8 GBps, peak bw / IB: no vote */
<2000000 0>; /* avg bw / AB: 16 GBps, peak bw / IB: no vote */
qcom,iommu-group = <&mhi0_iommu_group>;
#address-cells = <1>;
#size-cells = <1>;
mhi0_iommu_group: mhi0_iommu_group {
qcom,iommu-msi-size = <0x1000>;
qcom,iommu-dma-addr-pool = <0x20000000 0x0fffffff>;
qcom,iommu-dma = "fastmap";
qcom,iommu-pagetable = "coherent";
};
};
};

12
qcom/waipio-mtp-pm8008-overlay.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
#include "waipio-mtp.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio MTP with PM8008";
compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
qcom,board-id = <0x10008 0>;
};

11
qcom/waipio-mtp-pm8008.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio.dtsi"
#include "waipio-mtp.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio MTP with PM8008";
compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
qcom,board-id = <8 0>;
};

12
qcom/waipio-mtp-pm8010-overlay.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
#include "waipio-mtp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio MTP with PM8010";
compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
qcom,board-id = <0x10008 0>;
};

11
qcom/waipio-mtp-pm8010.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio.dtsi"
#include "waipio-mtp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio MTP with PM8010";
compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
qcom,board-id = <0x10008 0>;
};

182
qcom/waipio-mtp.dtsi Normal file
View File

@@ -0,0 +1,182 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "waipio-pmic-overlay.dtsi"
#include "waipio-thermal-overlay.dtsi"
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-waipio";
vdda-phy-supply = <&pm8350_l5>;
vdda-pll-supply = <&pm8350_l6>;
vdda-phy-max-microamp = <173000>;
vdda-pll-max-microamp = <24900>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&pm8350_l7>;
vcc-max-microamp = <1100000>;
vccq-supply = <&pm8350_l9>;
vccq-max-microamp = <1200000>;
qcom,vddp-ref-clk-supply = <&pm8350_l9>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq-parent-supply = <&pm8350_s12>;
qcom,vccq-parent-max-microamp = <210000>;
status = "ok";
};
&sdhc_2 {
status = "ok";
vdd-supply = <&pm8350c_l9>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&pm8350c_l6>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
};
&soc {
gpio_keys {
compatible = "gpio-keys";
label = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_vol_up_default>;
vol_up {
label = "volume_up";
gpios = <&pm8350_gpios 6 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
debounce-interval = <15>;
linux,can-disable;
};
};
};
&pm8350b_haptics {
status = "ok";
};
&pm8350c_switch0 {
qcom,led-mask = <9>; /* Channels 1 & 4 */
qcom,symmetry-en;
};
&pm8350c_switch1 {
qcom,led-mask = <6>; /* Channels 2 & 3 */
qcom,symmetry-en;
};
&pm8350c_switch2 {
qcom,led-mask = <15>; /* All Channels */
qcom,symmetry-en;
};
&pm8350c_flash {
status = "ok";
};
&battery_charger {
qcom,thermal-mitigation = <3000000 1500000 1000000 500000>;
qcom,wireless-fw-name = "idt9415.bin";
};
&qupv3_se9_i2c {
status = "ok";
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 46 0x00>;
qcom,sn-ven = <&tlmm 34 0x00>;
qcom,sn-firm = <&tlmm 45 0x00>;
qcom,sn-clkreq = <&tlmm 35 0x00>;
qcom,sn-vdd-1p8-supply = <&S10B>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <46 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};
&qupv3_se4_i2c {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
qcom,i2c-touch-active = "focaltech,fts_ts";
focaltech@38 {
compatible = "focaltech,fts_ts";
reg = <0x38>;
interrupt-parent = <&tlmm>;
interrupts = <21 0x2008>;
focaltech,reset-gpio = <&tlmm 20 0x00>;
focaltech,irq-gpio = <&tlmm 21 0x2008>;
focaltech,max-touch-number = <5>;
focaltech,display-coords = <0 0 1080 2340>;
focaltech,touch-type = "primary";
vdd-supply = <&L3C>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "pvm";
focaltech,trusted-touch-spi-irq = <754>;
focaltech,trusted-touch-io-bases = <0xF110000 0xF111000 0xF112000 0xF113000
0xF114000 0xF115000 0x990000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000
0x1000 0x1000 0x1000 0x4000>;
};
};
&usb0 {
usb-role-switch;
dwc3@a600000 {
usb-role-switch;
dr_mode = "otg";
};
port {
usb_port0: endpoint {
remote-endpoint = <&usb_port0_connector>;
};
};
};
&ucsi {
connector {
port {
usb_port0_connector: endpoint {
remote-endpoint = <&usb_port0>;
};
};
};
};

562
qcom/waipio-pcie.dtsi Normal file
View File

@@ -0,0 +1,562 @@
#include <dt-bindings/clock/qcom,gcc-waipio.h>
&soc {
pcie0: qcom,pcie@1c00000 {
compatible = "qcom,pci-msm";
reg = <0x01c00000 0x3000>,
<0x01c06000 0x2000>,
<0x60000000 0xf1d>,
<0x60000f20 0xa8>,
<0x60001000 0x1000>,
<0x60100000 0x100000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
cell-index = <0>;
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
interrupt-parent = <&pcie0>;
interrupts = <0 1 2 3 4>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
msi-map = <0x0 &gic_its 0x5980 0x1>, /* ITS IRQ 0x5980 */
<0x100 &gic_its 0x5981 0x20>; /* ITS IRQ 0x5981 - 0x59a1 */
perst-gpio = <&tlmm 94 0>;
wake-gpio = <&tlmm 96 0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_perst_default
&pcie0_clkreq_default
&pcie0_wake_default>;
pinctrl-1 = <&pcie0_perst_default
&pcie0_clkreq_sleep
&pcie0_wake_default>;
gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;
vreg-1p8-supply = <&pm8350_l6>;
vreg-0p9-supply = <&pm8350_l5>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
vreg-mx-supply = <&VDD_MXA_LEVEL>;
qcom,vreg-1p8-voltage-level = <1200000 1200000 18200>;
qcom,vreg-0p9-voltage-level = <880000 880000 80900>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_NOM 0>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_NOM
RPMH_REGULATOR_LEVEL_NOM
100000000>;
interconnect-names = "icc_path";
interconnects = <&pcie_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,
<&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_PCIE_0_AUX_CLK>,
<&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&clock_gcc GCC_PCIE_0_CLKREF_EN>,
<&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
<&clock_gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<&clock_gcc GCC_PCIE_0_PIPE_CLK_SRC>,
<&clock_gcc PCIE_0_PIPE_CLK>;
clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
"pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_0_axi_clk",
"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src";
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>,
<0>, <0>, <0>, <0>;
resets = <&clock_gcc GCC_PCIE_0_BCR>,
<&clock_gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "pcie_0_core_reset",
"pcie_0_phy_reset";
dma-coherent;
qcom,smmu-sid-base = <0x1c00>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
qcom,drv-supported;
qcom,drv-l1ss-timeout-us = <5000>;
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <150>;
qcom,slv-addr-space-size = <0x4000000>;
qcom,ep-latency = <10>;
qcom,num-parf-testbus-sel = <0xb9>;
qcom,pcie-phy-ver = <104>;
qcom,phy-status-offset = <0x214>;
qcom,phy-status-bit = <6>;
qcom,phy-power-down-offset = <0x240>;
qcom,phy-sequence = <0x0240 0x03 0x0
0x0094 0x08 0x0
0x0154 0x34 0x0
0x016c 0x08 0x0
0x0058 0x0f 0x0
0x00a4 0x42 0x0
0x0110 0x24 0x0
0x011c 0x03 0x0
0x0118 0xb4 0x0
0x010c 0x02 0x0
0x01bc 0x11 0x0
0x00bc 0x82 0x0
0x00d4 0x03 0x0
0x00d0 0x55 0x0
0x00cc 0x55 0x0
0x00b0 0x1a 0x0
0x00ac 0x0a 0x0
0x00c4 0x68 0x0
0x00e0 0x02 0x0
0x00dc 0xaa 0x0
0x00d8 0xab 0x0
0x00b8 0x34 0x0
0x00b4 0x14 0x0
0x0158 0x01 0x0
0x0074 0x06 0x0
0x007c 0x16 0x0
0x0084 0x36 0x0
0x0078 0x06 0x0
0x0080 0x16 0x0
0x0088 0x36 0x0
0x01b0 0x1e 0x0
0x01ac 0xca 0x0
0x01b8 0x18 0x0
0x01b4 0xa2 0x0
0x0050 0x07 0x0
0x0010 0x01 0x0
0x001c 0x31 0x0
0x0020 0x01 0x0
0x0024 0xde 0x0
0x0028 0x07 0x0
0x0030 0x4c 0x0
0x0034 0x06 0x0
0x0ee4 0x20 0x0
0x0e84 0x75 0x0
0x0e90 0x3f 0x0
0x115c 0x7f 0x0
0x1160 0xff 0x0
0x1164 0xbf 0x0
0x1168 0x3f 0x0
0x116c 0xd8 0x0
0x1170 0xdc 0x0
0x1174 0xdc 0x0
0x1178 0x5c 0x0
0x117c 0x34 0x0
0x1180 0xa6 0x0
0x1190 0x34 0x0
0x1194 0x38 0x0
0x10d8 0x07 0x0
0x0e3c 0x16 0x0
0x0e40 0x04 0x0
0x10dc 0x00 0x0
0x104c 0x08 0x0
0x1050 0x08 0x0
0x1044 0xf0 0x0
0x11a4 0x38 0x0
0x10cc 0xf0 0x0
0x10f4 0x07 0x0
0x1008 0x09 0x0
0x1014 0x05 0x0
0x0694 0x00 0x0
0x0654 0x00 0x0
0x06a8 0x0f 0x0
0x0048 0x90 0x0
0x0620 0xc1 0x0
0x0388 0x77 0x0
0x0398 0x0b 0x0
0x02dc 0x05 0x0
0x0200 0x00 0x0
0x0244 0x03 0x0>;
pcie0_rp: pcie0_rp {
reg = <0 0 0 0 0>;
};
};
pcie0_msi: qcom,pcie0_msi@0x17110040 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0x17110040 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
pcie1: qcom,pcie@1c08000 {
compatible = "qcom,pci-msm";
reg = <0x01c08000 0x3000>,
<0x01c0e000 0x2000>,
<0x40000000 0xf1d>,
<0x40000f20 0xa8>,
<0x40001000 0x1000>,
<0x40100000 0x100000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
cell-index = <1>;
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
interrupt-parent = <&pcie1>;
interrupts = <0 1 2 3 4>;
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
"int_d";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0xffffffff>;
interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
msi-parent = <&pcie1_msi>;
perst-gpio = <&tlmm 97 0>;
wake-gpio = <&tlmm 99 0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_perst_default
&pcie1_clkreq_default
&pcie1_wake_default>;
gdsc-vdd-supply = <&gcc_pcie_1_gdsc>;
vreg-1p8-supply = <&pm8350_l6>;
vreg-0p9-supply = <&pm8450_l2>;
vreg-cx-supply = <&VDD_CX_LEVEL>;
vreg-mx-supply = <&VDD_MXA_LEVEL>;
qcom,target-link-speed = <3>; /* Set max link speed to Gen3 */
qcom,vreg-1p8-voltage-level = <1200000 1200000 26100>;
qcom,vreg-0p9-voltage-level = <880000 912000 193000>;
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
RPMH_REGULATOR_LEVEL_LOW_SVS 0>;
qcom,bw-scale = /* Gen1 */
<RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen2 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
19200000
/* Gen3 */
RPMH_REGULATOR_LEVEL_LOW_SVS
RPMH_REGULATOR_LEVEL_LOW_SVS
100000000>;
interconnect-names = "icc_path";
interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>,
<&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_PCIE_1_AUX_CLK>,
<&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>,
<&clock_gcc GCC_PCIE_1_CLKREF_EN>,
<&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
<&clock_gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
<&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<&clock_gcc GCC_PCIE_1_PIPE_CLK_SRC>,
<&clock_gcc PCIE_1_PIPE_CLK>,
<&clock_gcc GCC_PCIE_1_PHY_AUX_CLK>;
clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
"pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
"pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
"pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
"pcie_phy_refgen_clk",
"pcie_ddrss_sf_tbu_clk",
"pcie_aggre_noc_1_axi_clk", "pcie_pipe_clk_mux",
"pcie_pipe_clk_ext_src", "pcie_phy_aux_clk";
max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
<0>, <0>, <0>, <0>, <100000000>, <0>,
<0>, <0>, <0>, <0>;
resets = <&clock_gcc GCC_PCIE_1_BCR>,
<&clock_gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "pcie_1_core_reset",
"pcie_1_phy_reset";
dma-coherent;
qcom,smmu-sid-base = <0x1c80>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>;
qcom,boot-option = <0x1>;
qcom,aux-clk-freq = <17>; /* 16.6 MHz */
qcom,eq-fmdc-t-min-phase23 = <1>;
qcom,slv-addr-space-size = <0x20000000>;
qcom,ep-latency = <10>;
qcom,num-parf-testbus-sel = <0xb9>;
qcom,l1-2-th-scale = <2>;
qcom,l1-2-th-value = <150>;
qcom,pcie-phy-ver = <105>;
qcom,phy-status-offset = <0x1214>;
qcom,phy-status-bit = <7>;
qcom,phy-power-down-offset = <0x1240>;
qcom,phy-sequence = <0x1240 0x03 0x0
0x101c 0x31 0x0
0x1020 0x01 0x0
0x1024 0xde 0x0
0x1028 0x07 0x0
0x1030 0x97 0x0
0x1034 0x0c 0x0
0x1044 0x14 0x0
0x1048 0x90 0x0
0x1058 0x0f 0x0
0x1074 0x06 0x0
0x1078 0x06 0x0
0x107c 0x16 0x0
0x1080 0x16 0x0
0x1084 0x36 0x0
0x1088 0x36 0x0
0x1094 0x08 0x0
0x10a4 0x46 0x0
0x10a8 0x04 0x0
0x10ac 0x0a 0x0
0x10b0 0x1a 0x0
0x10b4 0x14 0x0
0x10b8 0x34 0x0
0x10bc 0x82 0x0
0x10c4 0xd0 0x0
0x10cc 0x55 0x0
0x10d0 0x55 0x0
0x10d4 0x03 0x0
0x10d8 0x55 0x0
0x10dc 0x55 0x0
0x10e0 0x05 0x0
0x110c 0x02 0x0
0x1154 0x34 0x0
0x1158 0x12 0x0
0x115c 0x00 0x0
0x1168 0x0a 0x0
0x116c 0x04 0x0
0x119c 0x88 0x0
0x1174 0x20 0x0
0x117c 0x06 0x0
0x11a0 0x14 0x0
0x11a8 0x0f 0x0
0x0220 0x16 0x0
0x03c0 0x38 0x0
0x0a20 0x16 0x0
0x0bc0 0x38 0x0
0x0364 0xcc 0x0
0x0368 0x12 0x0
0x036c 0xcc 0x0
0x0374 0x4a 0x0
0x0378 0x29 0x0
0x037c 0xc5 0x0
0x0380 0xad 0x0
0x0384 0xb6 0x0
0x0388 0xc0 0x0
0x038c 0x1f 0x0
0x0390 0xfb 0x0
0x0394 0x0f 0x0
0x0398 0xc7 0x0
0x039c 0xef 0x0
0x03a0 0xbf 0x0
0x03a4 0xa0 0x0
0x03a8 0x81 0x0
0x03ac 0xde 0x0
0x03b0 0x7f 0x0
0x0b64 0xcc 0x0
0x0b68 0x12 0x0
0x0b6c 0xcc 0x0
0x0b74 0x4a 0x0
0x0b78 0x29 0x0
0x0b7c 0xc5 0x0
0x0b80 0xad 0x0
0x0b84 0xb6 0x0
0x0b88 0xc0 0x0
0x0b8c 0x1f 0x0
0x0b90 0xfb 0x0
0x0b94 0x0f 0x0
0x0b98 0xc7 0x0
0x0b9c 0xef 0x0
0x0ba0 0xbf 0x0
0x0ba4 0xa0 0x0
0x0ba8 0x81 0x0
0x0bac 0xde 0x0
0x0bb0 0x7f 0x0
0x03b4 0x20 0x0
0x022c 0x3f 0x0
0x0230 0x37 0x0
0x0bb4 0x20 0x0
0x0a2c 0x3f 0x0
0x0a30 0x37 0x0
0x0078 0x05 0x0
0x007c 0xf6 0x0
0x0878 0x05 0x0
0x087c 0xf6 0x0
0x0290 0x05 0x0
0x0a90 0x05 0x0
0x03f8 0x1f 0x0
0x0400 0x1f 0x0
0x0408 0x1f 0x0
0x0410 0x1f 0x0
0x0418 0x1f 0x0
0x0420 0x1f 0x0
0x03f4 0x1f 0x0
0x03fc 0x1f 0x0
0x0404 0x1f 0x0
0x0bf8 0x1f 0x0
0x0c00 0x1f 0x0
0x0c08 0x1f 0x0
0x0c10 0x1f 0x0
0x0c18 0x1f 0x0
0x0c20 0x1f 0x0
0x0bf4 0x1f 0x0
0x0bfc 0x1f 0x0
0x0c04 0x1f 0x0
0x0208 0x0c 0x0
0x0a08 0x0c 0x0
0x020c 0x0a 0x0
0x0a0c 0x0a 0x0
0x02dc 0x0a 0x0
0x0adc 0x0a 0x0
0x0308 0x0b 0x0
0x0b08 0x0b 0x0
0x027c 0x10 0x0
0x0a7c 0x10 0x0
0x02b4 0x00 0x0
0x0ab4 0x00 0x0
0x02ec 0x0f 0x0
0x0aec 0x0f 0x0
0x02c4 0x00 0x0
0x02c8 0x1f 0x0
0x0ac4 0x00 0x0
0x0ac8 0x1f 0x0
0x0030 0x1a 0x0
0x0034 0x0c 0x0
0x0830 0x1a 0x0
0x0834 0x0c 0x0
0x141c 0xc1 0x0
0x1490 0x00 0x0
0x13e0 0x16 0x0
0x13e4 0x22 0x0
0x1508 0x02 0x0
0x14a0 0x16 0x0
0x1584 0x28 0x0
0x1370 0x2e 0x0
0x155c 0x2e 0x0
0x1388 0x99 0x0
0x1200 0x00 0x0
0x1244 0x03 0x0>;
pcie1_rp: pcie1_rp {
reg = <0 0 0 0 0>;
};
};
pcie1_msi: qcom,pcie1_msi@17110040 {
compatible = "qcom,pci-msi";
msi-controller;
reg = <0x17110040 0x0>;
interrupt-parent = <&intc>;
interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;
};
};

2897
qcom/waipio-pinctrl.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

224
qcom/waipio-pm8008.dtsi Normal file
View File

@@ -0,0 +1,224 @@
/* Waipio configurations for PM8008I and PM8008J connected via I2C */
/ {
qcom,pmic-id = <0x2f 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
qcom,pmic-id-size = <8>;
};
/*
* Each QUP device that's a parent to PMIC must be listed as a critical device
* to GCC.
*/
&clock_gcc {
qcom,critical-devices = <&qupv3_se5_i2c>;
};
&qupv3_se5_i2c {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
pm8008i@8 {
compatible = "qcom,i2c-pmic";
reg = <0x8>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pm8008i_active>;
pm8008-chip@900 {
compatible = "qcom,pm8008-chip";
reg = <0x900>;
PM8008I_EN: qcom,pm8008-chip-en {
regulator-name = "pm8008i-chip-en";
};
};
qcom,revid@100 {
compatible = "qcom,qpnp-revid";
reg = <0x100>;
};
};
pm8008i@9 {
compatible = "qcom,i2c-pmic";
reg = <0x9>;
#address-cells = <1>;
#size-cells = <0>;
qcom,pm8008i-regulator {
compatible = "qcom,pm8008-regulator";
#address-cells = <1>;
#size-cells = <0>;
pm8008_en-supply = <&PM8008I_EN>;
vdd_l1_l2-supply = <&S12B>;
vdd_l3_l4-supply = <&BOB>;
vdd_l5-supply = <&S1C>;
vdd_l6-supply = <&BOB>;
vdd_l7-supply = <&BOB>;
L1I: pm8008i_l1: regulator@4000 {
reg = <0x4000>;
regulator-name = "pm8008i_l1";
regulator-min-microvolt = <480000>;
regulator-max-microvolt = <1104000>;
qcom,min-dropout-voltage = <24000>;
qcom,hpm-min-load = <30000>;
};
L2I: pm8008i_l2: regulator@4100 {
reg = <0x4100>;
regulator-name = "pm8008i_l2";
regulator-min-microvolt = <1056000>;
regulator-max-microvolt = <1056000>;
qcom,min-dropout-voltage = <56000>;
qcom,hpm-min-load = <30000>;
};
L3I: pm8008i_l3: regulator@4200 {
reg = <0x4200>;
regulator-name = "pm8008i_l3";
regulator-min-microvolt = <2784000>;
regulator-max-microvolt = <2904000>;
qcom,min-dropout-voltage = <224000>;
};
L4I: pm8008i_l4: regulator@4300 {
reg = <0x4300>;
regulator-name = "pm8008i_l4";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
qcom,min-dropout-voltage = <152000>;
};
L5I: pm8008i_l5: regulator@4400 {
reg = <0x4400>;
regulator-name = "pm8008i_l5";
regulator-min-microvolt = <1776000>;
regulator-max-microvolt = <1800000>;
qcom,min-dropout-voltage = <24000>;
};
L6I: pm8008i_l6: regulator@4500 {
reg = <0x4500>;
regulator-name = "pm8008i_l6";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
qcom,min-dropout-voltage = <208000>;
};
L7I: pm8008i_l7: regulator@4600 {
reg = <0x4600>;
regulator-name = "pm8008i_l7";
regulator-min-microvolt = <2712000>;
regulator-max-microvolt = <2960000>;
qcom,min-dropout-voltage = <296000>;
};
};
};
pm8008j@c {
compatible = "qcom,i2c-pmic";
reg = <0xc>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pm8008j_active>;
pm8008-chip@900 {
compatible = "qcom,pm8008-chip";
reg = <0x900>;
PM8008J_EN: qcom,pm8008-chip-en {
regulator-name = "pm8008j-chip-en";
};
};
qcom,revid@100 {
compatible = "qcom,qpnp-revid";
reg = <0x100>;
};
};
pm8008j@d {
compatible = "qcom,i2c-pmic";
reg = <0xd>;
#address-cells = <1>;
#size-cells = <0>;
qcom,pm8008j-regulator {
compatible = "qcom,pm8008-regulator";
#address-cells = <1>;
#size-cells = <0>;
pm8008_en-supply = <&PM8008J_EN>;
vdd_l1_l2-supply = <&S12B>;
vdd_l3_l4-supply = <&S1C>;
vdd_l5-supply = <&BOB>;
vdd_l6-supply = <&BOB>;
vdd_l7-supply = <&BOB>;
L1J: pm8008j_l1: regulator@4000 {
reg = <0x4000>;
regulator-name = "pm8008j_l1";
regulator-min-microvolt = <1104000>;
regulator-max-microvolt = <1104000>;
qcom,min-dropout-voltage = <64000>;
qcom,hpm-min-load = <30000>;
};
L2J: pm8008j_l2: regulator@4100 {
reg = <0x4100>;
regulator-name = "pm8008j_l2";
regulator-min-microvolt = <1056000>;
regulator-max-microvolt = <1056000>;
qcom,min-dropout-voltage = <24000>;
qcom,hpm-min-load = <30000>;
};
L3J: pm8008j_l3: regulator@4200 {
reg = <0x4200>;
regulator-name = "pm8008j_l3";
regulator-min-microvolt = <1576000>;
regulator-max-microvolt = <1800000>;
qcom,min-dropout-voltage = <224000>;
};
L4J: pm8008j_l4: regulator@4300 {
reg = <0x4300>;
regulator-name = "pm8008j_l4";
regulator-min-microvolt = <1608000>;
regulator-max-microvolt = <1800000>;
qcom,min-dropout-voltage = <192000>;
};
L5J: pm8008j_l5: regulator@4400 {
reg = <0x4400>;
regulator-name = "pm8008j_l5";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
qcom,min-dropout-voltage = <56000>;
};
L6J: pm8008j_l6: regulator@4500 {
reg = <0x4500>;
regulator-name = "pm8008j_l6";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
qcom,min-dropout-voltage = <120000>;
};
L7J: pm8008j_l7: regulator@4600 {
reg = <0x4600>;
regulator-name = "pm8008j_l7";
regulator-min-microvolt = <2912000>;
regulator-max-microvolt = <3304000>;
qcom,min-dropout-voltage = <96000>;
};
};
};
};

224
qcom/waipio-pm8010-i2c.dtsi Normal file
View File

@@ -0,0 +1,224 @@
/* Waipio configurations for PM8010I and PM8010J connected via I2C */
/ {
qcom,pmic-id = <0x2f 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
qcom,pmic-id-size = <8>;
};
/*
* Each QUP device that's a parent to PMIC must be listed as a critical device
* to GCC.
*/
&clock_gcc {
qcom,critical-devices = <&qupv3_se5_i2c>;
};
&qupv3_se5_i2c {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
pm8010i@8 {
compatible = "qcom,i2c-pmic";
reg = <0x8>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pm8008i_active>;
pm8010-chip@900 {
compatible = "qcom,pm8008-chip";
reg = <0x900>;
PM8010I_EN: qcom,pm8008-chip-en {
regulator-name = "pm8010i-chip-en";
};
};
qcom,revid@100 {
compatible = "qcom,qpnp-revid";
reg = <0x100>;
};
};
pm8010i@9 {
compatible = "qcom,i2c-pmic";
reg = <0x9>;
#address-cells = <1>;
#size-cells = <0>;
qcom,pm8010i-regulator {
compatible = "qcom,pm8010-regulator";
#address-cells = <1>;
#size-cells = <0>;
pm8008_en-supply = <&PM8010I_EN>;
vdd_l1_l2-supply = <&S12B>;
vdd_l3_l4-supply = <&BOB>;
vdd_l5-supply = <&S1C>;
vdd_l6-supply = <&BOB>;
vdd_l7-supply = <&BOB>;
L1I: pm8010i_l1: regulator@4000 {
reg = <0x4000>;
regulator-name = "pm8010i_l1";
regulator-min-microvolt = <480000>;
regulator-max-microvolt = <1104000>;
qcom,min-dropout-voltage = <24000>;
qcom,hpm-min-load = <30000>;
};
L2I: pm8010i_l2: regulator@4100 {
reg = <0x4100>;
regulator-name = "pm8010i_l2";
regulator-min-microvolt = <1056000>;
regulator-max-microvolt = <1056000>;
qcom,min-dropout-voltage = <56000>;
qcom,hpm-min-load = <30000>;
};
L3I: pm8010i_l3: regulator@4200 {
reg = <0x4200>;
regulator-name = "pm8010i_l3";
regulator-min-microvolt = <2784000>;
regulator-max-microvolt = <2904000>;
qcom,min-dropout-voltage = <224000>;
};
L4I: pm8010i_l4: regulator@4300 {
reg = <0x4300>;
regulator-name = "pm8010i_l4";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
qcom,min-dropout-voltage = <152000>;
};
L5I: pm8010i_l5: regulator@4400 {
reg = <0x4400>;
regulator-name = "pm8010i_l5";
regulator-min-microvolt = <1776000>;
regulator-max-microvolt = <1800000>;
qcom,min-dropout-voltage = <24000>;
};
L6I: pm8010i_l6: regulator@4500 {
reg = <0x4500>;
regulator-name = "pm8010i_l6";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
qcom,min-dropout-voltage = <208000>;
};
L7I: pm8010i_l7: regulator@4600 {
reg = <0x4600>;
regulator-name = "pm8010i_l7";
regulator-min-microvolt = <2712000>;
regulator-max-microvolt = <2960000>;
qcom,min-dropout-voltage = <296000>;
};
};
};
pm8010j@c {
compatible = "qcom,i2c-pmic";
reg = <0xc>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pm8008j_active>;
pm8010-chip@900 {
compatible = "qcom,pm8008-chip";
reg = <0x900>;
PM8010J_EN: qcom,pm8008-chip-en {
regulator-name = "pm8010j-chip-en";
};
};
qcom,revid@100 {
compatible = "qcom,qpnp-revid";
reg = <0x100>;
};
};
pm8010j@d {
compatible = "qcom,i2c-pmic";
reg = <0xd>;
#address-cells = <1>;
#size-cells = <0>;
qcom,pm8010j-regulator {
compatible = "qcom,pm8010-regulator";
#address-cells = <1>;
#size-cells = <0>;
pm8008_en-supply = <&PM8010J_EN>;
vdd_l1_l2-supply = <&S12B>;
vdd_l3_l4-supply = <&S1C>;
vdd_l5-supply = <&BOB>;
vdd_l6-supply = <&BOB>;
vdd_l7-supply = <&BOB>;
L1J: pm8010j_l1: regulator@4000 {
reg = <0x4000>;
regulator-name = "pm8010j_l1";
regulator-min-microvolt = <1104000>;
regulator-max-microvolt = <1104000>;
qcom,min-dropout-voltage = <64000>;
qcom,hpm-min-load = <30000>;
};
L2J: pm8010j_l2: regulator@4100 {
reg = <0x4100>;
regulator-name = "pm8010j_l2";
regulator-min-microvolt = <1056000>;
regulator-max-microvolt = <1056000>;
qcom,min-dropout-voltage = <24000>;
qcom,hpm-min-load = <30000>;
};
L3J: pm8010j_l3: regulator@4200 {
reg = <0x4200>;
regulator-name = "pm8010j_l3";
regulator-min-microvolt = <1576000>;
regulator-max-microvolt = <1800000>;
qcom,min-dropout-voltage = <224000>;
};
L4J: pm8010j_l4: regulator@4300 {
reg = <0x4300>;
regulator-name = "pm8010j_l4";
regulator-min-microvolt = <1608000>;
regulator-max-microvolt = <1800000>;
qcom,min-dropout-voltage = <192000>;
};
L5J: pm8010j_l5: regulator@4400 {
reg = <0x4400>;
regulator-name = "pm8010j_l5";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
qcom,min-dropout-voltage = <56000>;
};
L6J: pm8010j_l6: regulator@4500 {
reg = <0x4500>;
regulator-name = "pm8010j_l6";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
qcom,min-dropout-voltage = <120000>;
};
L7J: pm8010j_l7: regulator@4600 {
reg = <0x4600>;
regulator-name = "pm8010j_l7";
regulator-min-microvolt = <2912000>;
regulator-max-microvolt = <3304000>;
qcom,min-dropout-voltage = <96000>;
};
};
};
};

319
qcom/waipio-pm8010-spmi.dtsi Normal file
View File

@@ -0,0 +1,319 @@
/* Waipio configurations for PM8010I and PM8010J connected via SPMI */
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/spmi/spmi.h>
/ {
qcom,pmic-id = <0x2f 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x41 0x41>;
qcom,pmic-id-size = <10>;
};
&apps_rsc {
rpmh-regulator-ldoi2 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoi2";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L2I: pm8010i_l2: regulator-pm8010i-l2 {
regulator-name = "pm8010i_l2";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1056000>;
regulator-max-microvolt = <1056000>;
qcom,init-voltage = <1056000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldoi3 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoi3";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L3I: pm8010i_l3: regulator-pm8010i-l3 {
regulator-name = "pm8010i_l3";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2904000>;
regulator-max-microvolt = <2904000>;
qcom,init-voltage = <2904000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldoi4 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoi4";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L4I: pm8010i_l4: regulator-pm8010i-l4 {
regulator-name = "pm8010i_l4";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
qcom,init-voltage = <2800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldoi6 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoi6";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L6I: pm8010i_l6: regulator-pm8010i-l6 {
regulator-name = "pm8010i_l6";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
qcom,init-voltage = <2800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldoi7 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoi7";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L7I: pm8010i_l7: regulator-pm8010i-l7 {
regulator-name = "pm8010i_l7";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
qcom,init-voltage = <2960000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldoj1 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoj1";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L1J: pm8010j_l1: regulator-pm8010j-l1 {
regulator-name = "pm8010j_l1";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1104000>;
regulator-max-microvolt = <1104000>;
qcom,init-voltage = <1104000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldoj2 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoj2";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 30000>;
L2J: pm8010j_l2: regulator-pm8010j-l2 {
regulator-name = "pm8010j_l2";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1056000>;
regulator-max-microvolt = <1056000>;
qcom,init-voltage = <1056000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldoj3 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoj3";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L3J: pm8010j_l3: regulator-pm8010j-l3 {
regulator-name = "pm8010j_l3";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldoj4 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoj4";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L4J: pm8010j_l4: regulator-pm8010j-l4 {
regulator-name = "pm8010j_l4";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
qcom,init-voltage = <1800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldoj5 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoj5";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L5J: pm8010j_l5: regulator-pm8010j-l5 {
regulator-name = "pm8010j_l5";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
qcom,init-voltage = <2800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldoj6 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoj6";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L6J: pm8010j_l6: regulator-pm8010j-l6 {
regulator-name = "pm8010j_l6";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
qcom,init-voltage = <2800000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
rpmh-regulator-ldoj7 {
compatible = "qcom,rpmh-vrm-regulator";
qcom,resource-name = "ldoj7";
qcom,regulator-type = "pmic5-ldo";
qcom,supported-modes =
<RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
qcom,mode-threshold-currents = <0 10000>;
L7J: pm8010j_l7: regulator-pm8010j-l7 {
regulator-name = "pm8010j_l7";
qcom,set = <RPMH_REGULATOR_SET_ALL>;
regulator-min-microvolt = <3304000>;
regulator-max-microvolt = <3304000>;
qcom,init-voltage = <3304000>;
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&spmi_bus {
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
qcom,pm8010@8 {
compatible = "qcom,spmi-pmic";
reg = <8 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8010i_tz: qcom,temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x8 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
};
qcom,pm8010@9 {
compatible = "qcom,spmi-pmic";
reg = <9 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8010j_tz: qcom,temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x9 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
};
};
&thermal_zones {
pm8010i_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8010i_tz>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
pm8010j_tz {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-governor = "step_wise";
thermal-sensors = <&pm8010j_tz>;
trips {
trip0 {
temperature = <95000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <115000>;
hysteresis = <0>;
type = "critical";
};
trip2 {
temperature = <145000>;
hysteresis = <0>;
type = "critical";
};
};
};
};

467
qcom/waipio-pmic-overlay.dtsi Normal file
View File

@@ -0,0 +1,467 @@
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/iio/qcom,spmi-adc7-smb139x.h>
#include "pmk8350.dtsi"
#include "pm8350.dtsi"
#include "pm8350c.dtsi"
#include "pm8350b.dtsi"
#include "pmr735a.dtsi"
#include "pmr735b.dtsi"
#include "pm8450.dtsi"
&pmk8350 {
/delete-node/ pon_pbs@800;
/delete-node/ pon_hlos@1300;
pon_hlos@1300 {
compatible = "qcom,pm8998-pon";
reg = <0x1300>, <0x800>;
reg-names = "pon_hlos", "pon_pbs";
pwrkey {
compatible = "qcom,pmk8350-pwrkey";
interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_POWER>;
};
resin {
compatible = "qcom,pmk8350-resin";
interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
};
&pm8350_gpios {
pm8350_rear_tof_therm {
pm8350_rear_tof_therm_default: pm8350_rear_tof_therm_default {
pins = "gpio1";
bias-high-impedance;
};
};
key_vol_up {
key_vol_up_default: key_vol_up_default {
pins = "gpio6";
function = "normal";
input-enable;
bias-pull-up;
power-source = <1>;
};
};
};
&pm8350c_gpios {
lcd_backlight_ctrl {
lcd_backlight_ctrl_default: lcd_backlight_ctrl_default {
pins = "gpio8";
function = "func1";
input-disable;
output-enable;
bias-disable;
power-source = <1>; /* 1.8V */
qcom,drive-strength = <2>;
};
};
};
&pmk8350_sdam_2 {
hap_cl_brake: cl_brake@7c {
reg = <0x7c 0x1>;
bits = <0 8>;
};
};
&pm8350b_haptics {
nvmem-cell-names = "hap_cl_brake";
nvmem-cells = <&hap_cl_brake>;
nvmem-names = "hap_cfg_sdam";
nvmem = <&pmk8350_sdam_46>;
qcom,pbs-client = <&pm8350b_pbs2>;
};
&soc {
reboot_reason {
compatible = "qcom,reboot-reason";
nvmem-cells = <&restart_reason>;
nvmem-cell-names = "restart_reason";
};
pmic-pon-log {
compatible = "qcom,pmic-pon-log";
nvmem = <&pmk8350_sdam_5>;
nvmem-names = "pon_log";
};
};
&pmk8350_vadc {
pinctrl-names = "default";
pinctrl-0 = <&pm8350_rear_tof_therm_default>;
pm8350_msm_therm {
reg = <PM8350_ADC7_AMUX_THM1_100K_PU>;
label = "pm8350_msm_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm8350_cam_flash_therm {
reg = <PM8350_ADC7_AMUX_THM2_100K_PU>;
label = "pm8350_cam_flash_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm8350_hot_pocket_therm {
reg = <PM8350_ADC7_AMUX_THM3_100K_PU>;
label = "pm8350_hot_pocket_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm8350_wide_rfc_therm {
reg = <PM8350_ADC7_AMUX_THM4_100K_PU>;
label = "pm8350_wide_rfc_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm8350_rear_tof_therm {
reg = <PM8350_ADC7_AMUX_THM5_100K_PU>;
label = "pm8350_rear_tof_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm8350b_usb_conn_therm {
reg = <PM8350B_ADC7_AMUX_THM4_100K_PU>;
label = "pm8350b_usb_conn_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm8350b_wl_chg_therm {
reg = <PM8350B_ADC7_GPIO2_100K_PU>;
label = "pm8350b_wl_chg_therm";
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
pm8350b_chg_temp {
reg = <PM8350B_ADC7_CHG_TEMP>;
label = "pm8350b_chg_temp";
qcom,pre-scaling = <1 1>;
};
pm8350b_iin_fb {
reg = <PM8350B_ADC7_IIN_FB>;
label = "pm8350b_iin_fb";
qcom,pre-scaling = <32 100>;
};
pm8350b_ichg_fb {
reg = <PM8350B_ADC7_ICHG_FB>;
label = "pm8350b_ichg_fb";
qcom,pre-scaling = <1000 305185>;
};
pm8350b_usb_in_v_div_16 {
reg = <PM8350B_ADC7_USB_IN_V_16>;
label = "pm8350b_usb_in_v_div_16";
qcom,pre-scaling = <1 16>;
};
smb139x_1_smb_temp {
reg = <SMB1394_1_ADC7_SMB_TEMP>;
label = "smb139x_1_smb_temp";
qcom,pre-scaling = <1 1>;
};
smb139x_1_ichg_smb {
reg = <SMB1394_1_ADC7_ICHG_SMB>;
label = "smb139x_1_ichg_smb";
qcom,pre-scaling = <16 100>;
};
smb139x_1_iin_smb {
reg = <SMB1394_1_ADC7_IIN_SMB>;
label = "smb139x_1_iin_smb";
qcom,pre-scaling = <32 100>;
};
smb139x_2_smb_temp {
reg = <SMB1394_2_ADC7_SMB_TEMP>;
label = "smb139x_2_smb_temp";
qcom,pre-scaling = <1 1>;
};
smb139x_2_ichg_smb {
reg = <SMB1394_2_ADC7_ICHG_SMB>;
label = "smb139x_2_ichg_smb";
qcom,pre-scaling = <16 100>;
};
smb139x_2_iin_smb {
reg = <SMB1394_2_ADC7_IIN_SMB>;
label = "smb139x_2_iin_smb";
qcom,pre-scaling = <32 100>;
};
};
&pm8350_tz {
io-channels = <&pmk8350_vadc PM8350_ADC7_DIE_TEMP>;
io-channel-names = "thermal";
};
&pm8350b_tz {
io-channels = <&pmk8350_vadc PM8350B_ADC7_DIE_TEMP>;
io-channel-names = "thermal";
};
&pmr735a_tz {
io-channels = <&pmk8350_vadc PMR735A_ADC7_DIE_TEMP>;
io-channel-names = "thermal";
};
&pmr735b_tz {
io-channels = <&pmk8350_vadc PMR735B_ADC7_DIE_TEMP>;
io-channel-names = "thermal";
};
&pmk8350_adc_tm {
io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM1_100K_PU>,
<&pmk8350_vadc PM8350_ADC7_AMUX_THM2_100K_PU>,
<&pmk8350_vadc PM8350_ADC7_AMUX_THM3_100K_PU>,
<&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU>,
<&pmk8350_vadc PM8350_ADC7_AMUX_THM5_100K_PU>,
<&pmk8350_vadc PM8350B_ADC7_AMUX_THM4_100K_PU>,
<&pmk8350_vadc PM8350B_ADC7_GPIO2_100K_PU>,
<&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
pm8350_msm_therm {
reg = <PM8350_ADC7_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm8350_cam_flash_therm {
reg = <PM8350_ADC7_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm8350_hot_pocket_therm {
reg = <PM8350_ADC7_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm8350_wide_rfc_therm {
reg = <PM8350_ADC7_AMUX_THM4_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm8350_rear_tof_therm {
reg = <PM8350_ADC7_AMUX_THM5_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm8350b_usb_conn_therm {
reg = <PM8350B_ADC7_AMUX_THM4_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pm8350b_wl_chg_therm {
reg = <PM8350B_ADC7_GPIO2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
pmk8350_xo_therm {
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&thermal_zones {
skin-msm-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM1_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
camera-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM2_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
hot-pock-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM3_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
rear-cam-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM4_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
tof-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PM8350_ADC7_AMUX_THM5_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
conn-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PM8350B_ADC7_AMUX_THM4_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
wlc-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PM8350B_ADC7_GPIO2_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
xo-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>;
trips {
active-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
active-config1 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
xo_config0: xo-config0 {
temperature = <78000>;
hysteresis = <8000>;
type = "passive";
};
xo_config1: xo-config1 {
temperature = <80000>;
hysteresis = <10000>;
type = "passive";
};
xo_config2: xo-config2 {
temperature = <90000>;
hysteresis = <10000>;
type = "critical";
};
};
};
};

8
qcom/waipio-qrd-2s.dtsi Normal file
View File

@@ -0,0 +1,8 @@
#include "waipio-qrd.dtsi"
&battery_charger {
qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000
7500000 7000000 6500000 6000000 5500000
5000000 4500000 4000000 3500000 3000000
2500000 2000000 1500000 1000000 500000>;
};

12
qcom/waipio-qrd-pm8008-overlay.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
#include "waipio-qrd.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio QRD with PM8008";
compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
qcom,board-id = <0x1000B 0>;
};

11
qcom/waipio-qrd-pm8008.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio.dtsi"
#include "waipio-qrd.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio QRD with PM8008";
compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
qcom,board-id = <11 0>;
};

12
qcom/waipio-qrd-pm8010-2s-overlay.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
#include "waipio-qrd-2s.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio QRD with PM8010 + 2S";
compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
qcom,board-id = <0x2000b 0>;
};

11
qcom/waipio-qrd-pm8010-2s.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio.dtsi"
#include "waipio-qrd-2s.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio QRD with PM8010 + 2S";
compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
qcom,board-id = <0x2000b 0>;
};

12
qcom/waipio-qrd-pm8010-overlay.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
#include "waipio-qrd.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio QRD with PM8010";
compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
qcom,msm-id = <457 0x10000>, <482 0x10000>, <457 0x20000>, <482 0x20000>;
qcom,board-id = <0x1000b 0>;
};

11
qcom/waipio-qrd-pm8010.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio.dtsi"
#include "waipio-qrd.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio QRD with PM8010";
compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
qcom,board-id = <0x1000b 0>;
};

277
qcom/waipio-qrd.dtsi Normal file
View File

@@ -0,0 +1,277 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "waipio-pmic-overlay.dtsi"
#include "waipio-thermal-overlay.dtsi"
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-waipio";
vdda-phy-supply = <&pm8350_l5>;
vdda-pll-supply = <&pm8350_l6>;
vdda-phy-max-microamp = <173000>;
vdda-pll-max-microamp = <24900>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vcc-supply = <&pm8350_l7>;
vcc-max-microamp = <1100000>;
vccq-supply = <&pm8350_l9>;
vccq-max-microamp = <1200000>;
qcom,vddp-ref-clk-supply = <&pm8350_l9>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,vccq-parent-supply = <&pm8350_s12>;
qcom,vccq-parent-max-microamp = <210000>;
status = "ok";
};
&sdhc_2 {
vdd-supply = <&pm8350c_l9>;
qcom,vdd-voltage-level = <2960000 2960000>;
qcom,vdd-current-level = <0 800000>;
vdd-io-supply = <&pm8350c_l6>;
qcom,vdd-io-voltage-level = <1800000 2960000>;
qcom,vdd-io-current-level = <0 22000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
status = "ok";
};
&qupv3_se5_i2c {
status = "ok";
};
&soc {
gpio_keys {
compatible = "gpio-keys";
label = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&key_vol_up_default>;
vol_up {
label = "volume_up";
gpios = <&pm8350_gpios 6 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
debounce-interval = <15>;
linux,can-disable;
};
};
};
&pm8350b_haptics {
qcom,vmax-mv = <1300>;
qcom,lra-period-us = <5880>;
status = "ok";
effect_0 {
/* CLICK */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
effect_1 {
/* DOUBLE_CLICK */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
effect_2 {
/* TICK */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
effect_3 {
/* THUD */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
effect_4 {
/* POP */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
effect_5 {
/* HEAVY CLICK */
qcom,wf-vmax-mv = <1800>;
qcom,wf-pattern-period-us = <5880>;
};
};
&pm8350c_switch0 {
qcom,led-mask = <9>; /* Channels 1 & 4 */
qcom,symmetry-en;
};
&pm8350c_switch1 {
qcom,led-mask = <6>; /* Channels 2 & 3 */
qcom,symmetry-en;
};
&pm8350c_switch2 {
qcom,led-mask = <15>; /* All Channels */
qcom,symmetry-en;
};
&pm8350c_flash {
status = "ok";
};
&battery_charger {
qcom,thermal-mitigation = <11500000 11000000 10500000 10000000 9500000
9000000 8500000 8000000 7500000 7000000 6500000
6000000 5500000 5000000 4500000 4000000 3500000
3000000 2500000 2000000 1500000 1000000 500000>;
qcom,wireless-fw-name = "idt9415.bin";
};
&qupv3_se9_i2c {
status = "ok";
qcom,clk-freq-out = <1000000>;
#address-cells = <1>;
#size-cells = <0>;
nq@28 {
compatible = "qcom,sn-nci";
reg = <0x28>;
qcom,sn-irq = <&tlmm 46 0x00>;
qcom,sn-ven = <&tlmm 34 0x00>;
qcom,sn-firm = <&tlmm 45 0x00>;
qcom,sn-clkreq = <&tlmm 35 0x00>;
qcom,sn-vdd-1p8-supply = <&S10B>;
qcom,sn-vdd-1p8-voltage = <1800000 1800000>;
qcom,sn-vdd-1p8-current = <157000>;
interrupt-parent = <&tlmm>;
interrupts = <46 0>;
interrupt-names = "nfc_irq";
pinctrl-names = "nfc_active", "nfc_suspend";
pinctrl-0 = <&nfc_int_active &nfc_enable_active>;
pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
};
};
&qupv3_se4_spi {
status = "ok";
qcom,spi-touch-active = "focaltech,fts_ts";
qcom,la-vm;
focaltech@0 {
compatible = "focaltech,fts_ts";
reg = <0x0>;
spi-max-frequency = <6000000>;
interrupt-parent = <&tlmm>;
interrupts = <21 0x2008>;
focaltech,reset-gpio = <&tlmm 20 0x00>;
focaltech,irq-gpio = <&tlmm 21 0x2008>;
focaltech,display-coords = <0 0 1080 2340>;
focaltech,max-touch-number = <5>;
focaltech,ic-type = <0x3658D488>;
focaltech,touch-type = "primary";
vdd-supply = <&L3C>;
pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", "pmx_ts_release";
pinctrl-0 = <&ts_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
pinctrl-2 = <&ts_release>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "pvm";
focaltech,trusted-touch-spi-irq = <754>;
focaltech,trusted-touch-io-bases = <0xF110000 0xF111000 0xF112000 0xF113000 0xF114000 0xF115000 0x990000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
};
};
&qupv3_se5_i2c {
status = "ok";
#address-cells = <1>;
#size-cells = <0>;
redriver: redriver@1c {
compatible = "onnn,redriver";
reg = <0x1c>;
lane-channel-swap;
pinctrl-names = "default";
pinctrl-0 = <&usb3phy_portselect_gpio>;
gpios = <&tlmm 91 0>;
eq = /bits/ 8 <
/* Parameters for USB */
0x4 0x4 0x4 0x4
/* Parameters for DP */
0x6 0x4 0x4 0x6>;
flat-gain = /bits/ 8 <
/* Parameters for USB */
0x3 0x1 0x1 0x3
/* Parameters for DP */
0x2 0x1 0x1 0x2>;
output-comp = /bits/ 8 <
/* Parameters for USB */
0x3 0x3 0x3 0x3
/* Parameters for DP */
0x3 0x3 0x3 0x3>;
loss-match = /bits/ 8 <
/* Parameters for USB */
0x1 0x3 0x3 0x1
/* Parameters for DP */
0x3 0x3 0x3 0x3>;
};
};
&usb_qmp_dp_phy {
pinctrl-names = "unused";
};
&usb0 {
usb-role-switch;
ssusb_redriver = <&redriver>;
dwc3@a600000 {
usb-role-switch;
dr_mode = "otg";
};
port {
usb_port0: endpoint {
remote-endpoint = <&usb_port0_connector>;
};
};
};
&usb2_phy0 {
qcom,param-override-seq =
<0xe6 0x6c
0x0c 0x70
0x17 0x74>;
};
&ucsi {
connector {
port {
usb_port0_connector: endpoint {
remote-endpoint = <&usb_port0>;
};
};
};
};

1114
qcom/waipio-qupv3.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

1058
qcom/waipio-regulators.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

11
qcom/waipio-rumi-overlay.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
/plugin/;
#include "waipio-rumi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio RUMI";
compatible = "qcom,waipio-rumi", "qcom,waipio", "qcom,rumi";
qcom,msm-id = <457 0x10000>;
qcom,board-id = <0x1000F 0>;
};

11
qcom/waipio-rumi.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
/memreserve/ 0x90000000 0x00010000;
#include "waipio.dtsi"
#include "waipio-rumi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio RUMI";
compatible = "qcom,waipio-rumi", "qcom,waipio", "qcom,rumi";
qcom,board-id = <15 0>;
};

135
qcom/waipio-rumi.dtsi Normal file
View File

@@ -0,0 +1,135 @@
#include <dt-bindings/gpio/gpio.h>
#include "waipio-pmic-overlay.dtsi"
&arch_timer {
clock-frequency = <500000>;
};
&memtimer {
clock-frequency = <500000>;
};
&soc {
pcie0: qcom,pcie@1c00000 {
reg = <0x01c00000 0x3000>,
<0x01c06000 0x2000>,
<0x60000000 0xf1d>,
<0x60000f20 0xa8>,
<0x60001000 0x1000>,
<0x60100000 0x100000>,
<0x01c05000 0x1000>;
reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
"rumi";
qcom,target-link-speed = <0x1>;
qcom,link-check-max-count = <200>; /* 1 sec */
qcom,no-l1-supported;
qcom,no-l1ss-supported;
qcom,no-aux-clk-sync;
status = "ok";
};
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
usb_emuphy: phy@a784000 {
compatible = "qcom,usb-emu-phy";
reg = <0x0a784000 0x9500>;
qcom,emu-init-seq = <0xfffff 0x4
0xffff0 0x4
0x100000 0x20
0x0 0x20
0x000101F0 0x20
0x00100000 0x3c
0x0 0x3c
0x0 0x4>;
};
};
&usb0 {
dwc3@a600000 {
usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
dr_mode = "peripheral";
maximum-speed = "high-speed";
};
};
&usb2_phy0 {
status = "disabled";
};
&usb_qmp_dp_phy {
status = "disabled";
};
&sdhc_2 {
status = "ok";
vdd-supply = <&pm8350c_l9>;
qcom,vdd-voltage-level = <2950000 2960000>;
qcom,vdd-current-level = <200 800000>;
vdd-io-supply = <&pm8350c_l6>;
qcom,vdd-io-voltage-level = <2960000 2960000>;
qcom,vdd-io-current-level = <200 22000>;
cap-sd-highspeed;
max-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>;
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qrbtc-sdm845";
vdda-phy-supply = <&pm8350_l5>;
vdda-pll-supply = <&pm8350_l6>;
vdda-phy-max-microamp = <102000>;
vdda-pll-max-microamp = <19200>;
status = "ok";
};
&ufshc_mem {
limit-tx-hs-gear = <1>;
limit-rx-hs-gear = <1>;
limit-rate = <2>; /* HS Rate-B */
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vdd-hba-fixed-regulator;
vcc-supply = <&pm8350_l7>;
vcc-max-microamp = <1100000>;
vccq-supply = <&pm8350_l9>;
vccq-max-microamp = <1200000>;
qcom,vddp-ref-clk-supply = <&pm8350_l9>;
qcom,vddp-ref-clk-max-microamp = <100>;
qcom,disable-lpm;
rpm-level = <0>;
spm-level = <0>;
qcom,iommu-dma = "bypass";
status = "ok";
};
&qupv3_se5_i2c {
status = "disabled";
};
&tsens0 {
status = "disabled";
};
&tsens1 {
status = "disabled";
};

140
qcom/waipio-smp2p.dtsi Normal file
View File

@@ -0,0 +1,140 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,ipcc.h>
&soc {
qcom,smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
qcom,entry-name = "rdbg";
#qcom,smem-state-cells = <1>;
};
smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
qcom,entry-name = "rdbg";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-dsps {
compatible = "qcom,smp2p";
qcom,smem = <481>, <430>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
dsps_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
dsps_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
sleepstate_smp2p_out: sleepstate-out {
qcom,entry-name = "sleepstate";
#qcom,smem-state-cells = <1>;
};
sleepstate_smp2p_in: qcom,sleepstate-in {
qcom,entry-name = "sleepstate_see";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
qcom,entry-name = "rdbg";
#qcom,smem-state-cells = <1>;
};
smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
qcom,entry-name = "rdbg";
interrupt-controller;
#interrupt-cells = <2>;
};
};
qcom,smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupt-parent = <&ipcc_mproc>;
interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
/* ipa - inbound entry from mss */
smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

632
qcom/waipio-thermal-modem.dtsi Normal file
View File

@@ -0,0 +1,632 @@
#include <dt-bindings/thermal/thermal_qti.h>
&soc {
qmi-tmd-devices {
compatible = "qcom,qmi-cooling-devices";
modem {
qcom,instance-id = <QMI_MODEM_INST_ID>;
modem_lte_dsc: mmodem_lte_dsc {
qcom,qmi-dev-name = "modem_lte_dsc";
#cooling-cells = <2>;
};
modem_nr_dsc: modem_nr_dsc {
qcom,qmi-dev-name = "modem_nr_dsc";
#cooling-cells = <2>;
};
modem_nr_scg_dsc: modem_nr_scg_dsc {
qcom,qmi-dev-name = "modem_nr_scg_dsc";
#cooling-cells = <2>;
};
sdr0_lte_dsc: sdr0_lte_dsc {
qcom,qmi-dev-name = "sdr0_lte_dsc";
#cooling-cells = <2>;
};
sdr1_lte_dsc: sdr1_lte_dsc {
qcom,qmi-dev-name = "sdr1_lte_dsc";
#cooling-cells = <2>;
};
sdr0_nr_dsc: sdr0_nr_dsc {
qcom,qmi-dev-name = "sdr0_nr_dsc";
#cooling-cells = <2>;
};
sdr1_nr_dsc: sdr1_nr_dsc {
qcom,qmi-dev-name = "sdr1_nr_dsc";
#cooling-cells = <2>;
};
pa_sdr0_dsc: pa_sdr0_dsc {
qcom,qmi-dev-name = "pa_sdr0_dsc";
#cooling-cells = <2>;
};
pa_sdr1_dsc: pa_sdr1_dsc {
qcom,qmi-dev-name = "pa_sdr1_dsc";
#cooling-cells = <2>;
};
pa_fr1_sdr0_dsc: pa_fr1_sdr0_dsc {
qcom,qmi-dev-name = "pa_fr1_sdr0_dsc";
#cooling-cells = <2>;
};
pa_fr1_sdr1_dsc: pa_fr1_sdr1_dsc {
qcom,qmi-dev-name = "pa_fr1_sdr1_dsc";
#cooling-cells = <2>;
};
pa_fr1_sdr0_scg_dsc: pa_fr1_sdr0_scg_dsc {
qcom,qmi-dev-name = "pa_fr1_sdr0_scg_dsc";
#cooling-cells = <2>;
};
pa_fr1_sdr1_scg_dsc: pa_fr1_sdr1_scg_dsc {
qcom,qmi-dev-name = "pa_fr1_sdr1_scg_dsc";
#cooling-cells = <2>;
};
mmw0_dsc: mmw0_dsc {
qcom,qmi-dev-name = "mmw0_dsc";
#cooling-cells = <2>;
};
mmw1_dsc: mmw1_dsc {
qcom,qmi-dev-name = "mmw1_dsc";
#cooling-cells = <2>;
};
mmw2_dsc: mmw2_dsc {
qcom,qmi-dev-name = "mmw2_dsc";
#cooling-cells = <2>;
};
mmw3_dsc: mmw3_dsc {
qcom,qmi-dev-name = "mmw3_dsc";
#cooling-cells = <2>;
};
mmw_ul_throttle_dsc: mmw_ul_throttling_dsc {
qcom,qmi-dev-name = "mmw_ul_throttling_dsc";
#cooling-cells = <2>;
};
mmw_ific_dsc: mmw_ific_dsc {
qcom,qmi-dev-name = "mmw_ific_dsc";
#cooling-cells = <2>;
};
qmi_wlan: wlan {
qcom,qmi-dev-name = "wlan";
#cooling-cells = <2>;
};
wlan_bw: wlan_bw {
qcom,qmi-dev-name = "wlan_bw";
#cooling-cells = <2>;
};
modem_vdd: modem_vdd {
qcom,qmi-dev-name = "cpuv_restriction_cold";
#cooling-cells = <2>;
};
};
};
qmi_sensor: qmi-ts-sensors {
compatible = "qcom,qmi-sensors";
#thermal-sensor-cells = <1>;
modem {
qcom,instance-id = <QMI_MODEM_INST_ID>;
qcom,qmi-sensor-names = "pa",
"pa_1",
"qtm_therm",
"sys_therm1",
"sys_therm2",
"modem_bcl_warn",
"modem_tsens",
"modem_tsens1",
"sdr0_pa0",
"sdr0_pa1",
"sdr0_pa2",
"sdr0_pa3",
"sdr0_pa4",
"sdr0",
"sdr1_pa0",
"sdr1_pa1",
"sdr1_pa2",
"sdr1_pa3",
"sdr1_pa4",
"sdr1_pa5",
"sdr1",
"mmw0",
"mmw1",
"mmw2",
"mmw3",
"mmw_ific0";
};
};
};
&thermal_zones {
pa {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_PA)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
pa1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_PA_1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
qtm-therm {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_QTM_THERM)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SYS_THERM_1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sys-therm2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SYS_THERM_2)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
bcl-warn {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_BCL_WARN)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr0-pa0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR0_PA0)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr0-pa1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR0_PA1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr0-pa2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR0_PA2)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr0-pa3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR0_PA3)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr0-pa4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR0_PA4)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR0)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr1-pa0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR1_PA0)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr1-pa1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR1_PA1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr1-pa2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR1_PA2)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr1-pa3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR1_PA3)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr1-pa4 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR1_PA4)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr1-pa5 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR1_PA5)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
sdr1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_SDR1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MMW0)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw1 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MMW1)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw2 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MMW2)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw3 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MMW3)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
thermal-hal-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
mmw-ific0 {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&qmi_sensor
(QMI_MODEM_INST_ID+QMI_MMW_IFIC0)>;
trips {
thermal-engine-config0 {
temperature = <125000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};

262
qcom/waipio-thermal-overlay.dtsi Normal file
View File

@@ -0,0 +1,262 @@
#include <dt-bindings/thermal/thermal_qti.h>
&thermal_zones {
socd {
cooling-maps {
socd_apc1 {
trip = <&socd_trip>;
cooling-device = <&APC1_pause 1 1>;
};
socd_cdsp1 {
trip = <&socd_trip>;
cooling-device = <&cdsp_sw 4 4>;
};
socd_gpu0 {
trip = <&socd_trip>;
cooling-device = <&msm_gpu 4 4>;
};
};
};
pm8350b-bcl-lvl0 {
cooling-maps {
vbat_cpu_5 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cpu5_pause 1 1>;
};
vbat_gpu0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&msm_gpu 2 2>;
};
vbat_cdsp0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&cdsp_sw 2 2>;
};
vbat_lte0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_lte_dsc 255 255>;
};
vbat_nr0 {
trip = <&b_bcl_lvl0>;
cooling-device = <&modem_nr_scg_dsc 255 255>;
};
};
};
pm8350b-bcl-lvl1 {
cooling-maps {
vbat_cpu_6_7 {
trip = <&b_bcl_lvl1>;
cooling-device = <&cpu_6_7_pause 1 1>;
};
vbat_gpu1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&msm_gpu 4 4>;
};
vbat_cdsp1 {
trip = <&b_bcl_lvl1>;
cooling-device = <&cdsp_sw 4 4>;
};
};
};
pm8350b-bcl-lvl2 {
cooling-maps {
vbat_gpu2 {
trip = <&b_bcl_lvl2>;
cooling-device = <&msm_gpu 7 THERMAL_NO_LIMIT>;
};
vbat_cdsp2 {
trip = <&b_bcl_lvl2>;
cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
};
};
};
pm8350c-bcl-lvl0 {
cooling-maps {
vph_cpu_5 {
trip = <&c_bcl_lvl0>;
cooling-device = <&cpu5_pause 1 1>;
};
vph_gpu0 {
trip = <&c_bcl_lvl0>;
cooling-device = <&msm_gpu 2 2>;
};
vph_cdsp0 {
trip = <&c_bcl_lvl0>;
cooling-device = <&cdsp_sw 2 2>;
};
vph_lte0 {
trip = <&c_bcl_lvl0>;
cooling-device = <&modem_lte_dsc 255 255>;
};
vph_nr0 {
trip = <&c_bcl_lvl0>;
cooling-device = <&modem_nr_scg_dsc 255 255>;
};
};
};
pm8350c-bcl-lvl1 {
cooling-maps {
vph_cpu_6_7 {
trip = <&c_bcl_lvl1>;
cooling-device = <&cpu_6_7_pause 1 1>;
};
vph_gpu1 {
trip = <&c_bcl_lvl1>;
cooling-device = <&msm_gpu 4 4>;
};
vph_cdsp1 {
trip = <&c_bcl_lvl1>;
cooling-device = <&cdsp_sw 4 4>;
};
};
};
pm8350c-bcl-lvl2 {
cooling-maps {
vph_gpu2 {
trip = <&c_bcl_lvl2>;
cooling-device = <&msm_gpu 7 THERMAL_NO_LIMIT>;
};
vph_cdsp2 {
trip = <&c_bcl_lvl2>;
cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
};
};
};
pm8450_tz {
cooling-maps {
pm8450_cpu4_freq {
trip = <&pm8450_trip0>;
cooling-device = <&CPU4 15 THERMAL_NO_LIMIT>;
};
pm8450_cpu7_freq {
trip = <&pm8450_trip0>;
cooling-device = <&CPU7 15 THERMAL_NO_LIMIT>;
};
pm8450_apc1 {
trip = <&pm8450_trip0>;
cooling-device = <&APC1_pause 1 1>;
};
};
};
pm8350_tz {
cooling-maps {
pm8350_gpu {
trip = <&pm8350_trip0>;
cooling-device = <&msm_gpu 7 THERMAL_NO_LIMIT>;
};
pm8350_cpu4_freq {
trip = <&pm8350_trip0>;
cooling-device = <&CPU4 15 THERMAL_NO_LIMIT>;
};
pm8350_cpu7_freq {
trip = <&pm8350_trip0>;
cooling-device = <&CPU7 15 THERMAL_NO_LIMIT>;
};
pm8350_apc1 {
trip = <&pm8350_trip0>;
cooling-device = <&APC1_pause 1 1>;
};
};
};
pm8350c_tz {
cooling-maps {
pm8350c_nsp {
trip = <&pm8350c_trip0>;
cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
};
pm8350c_lte {
trip = <&pm8350c_trip0>;
cooling-device = <&modem_lte_dsc 255 255>;
};
pm8350c_nr {
trip = <&pm8350c_trip0>;
cooling-device = <&modem_nr_scg_dsc 255 255>;
};
};
};
xo-therm {
cooling-maps {
cpu4_freq_cdev {
trip = <&xo_config0>;
cooling-device = <&CPU4 15 THERMAL_NO_LIMIT>;
};
cpu7_freq_cdev {
trip = <&xo_config0>;
cooling-device = <&CPU7 15 THERMAL_NO_LIMIT>;
};
apc1_cdev {
trip = <&xo_config0>;
cooling-device = <&APC1_pause 1 1>;
};
cdsp_cdev {
trip = <&xo_config0>;
cooling-device = <&cdsp_sw 5 THERMAL_NO_LIMIT>;
};
gpu_cdev {
trip = <&xo_config0>;
cooling-device = <&msm_gpu 7 THERMAL_NO_LIMIT>;
};
cpu5_hot_cdev {
trip = <&xo_config1>;
cooling-device = <&cpu5_hotplug 1 1>;
};
cpu6_hot_cdev {
trip = <&xo_config1>;
cooling-device = <&cpu6_hotplug 1 1>;
};
cpu7_hot_cdev {
trip = <&xo_config1>;
cooling-device = <&cpu7_hotplug 1 1>;
};
lte_cdev {
trip = <&xo_config1>;
cooling-device = <&modem_lte_dsc 255 255>;
};
nr_cdev {
trip = <&xo_config1>;
cooling-device = <&modem_nr_scg_dsc 255 255>;
};
};
};
};

1412
qcom/waipio-thermal.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

335
qcom/waipio-usb.dtsi Normal file
View File

@@ -0,0 +1,335 @@
#include <dt-bindings/clock/qcom,gcc-waipio.h>
#include <dt-bindings/phy/qcom,usb3-5nm-qmp-combo.h>
&soc {
usb0: ssusb@a600000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0xa600000 0x100000>;
reg-names = "core_base";
#address-cells = <1>;
#size-cells = <1>;
ranges;
USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>,
<&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>,
<&clock_gcc GCC_USB3_0_CLKREF_EN>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk", "xo";
resets = <&clock_gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset";
interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 15 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
"ss_phy_irq", "dm_hs_phy_irq";
qcom,use-pdc-interrupts;
qcom,core-clk-rate = <200000000>;
qcom,core-clk-rate-hs = <66666667>;
qcom,num-gsi-evt-buffs = <0x3>;
qcom,gsi-reg-offset =
<0x0fc /* GSI_GENERAL_CFG */
0x110 /* GSI_DBL_ADDR_L */
0x120 /* GSI_DBL_ADDR_H */
0x130 /* GSI_RING_BASE_ADDR_L */
0x144 /* GSI_RING_BASE_ADDR_H */
0x1a4>; /* GSI_IF_STS */
qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
extcon = <&eud>;
dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xd93c>;
iommus = <&apps_smmu 0x0 0x0>;
qcom,iommu-dma = "atomic";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
dma-coherent;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,is-utmi-l1-suspend;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis_u2_susphy_quirk;
snps,ssp-u3-u0-quirk;
tx-fifo-resize;
dr_mode = "otg";
maximum-speed = "super-speed-plus";
usb-role-switch;
};
qcom,usbbam@a704000 {
compatible = "qcom,usb-bam-msm";
reg = <0xa704000 0x18000>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
qcom,usb-bam-fifo-baseaddr = <0x146a6000>;
qcom,usb-bam-num-pipes = <4>;
qcom,disable-clk-gating;
qcom,usb-bam-override-threshold = <0x4001>;
qcom,usb-bam-max-mbps-highspeed = <400>;
qcom,usb-bam-max-mbps-superspeed = <3600>;
qcom,reset-bam-on-connect;
qcom,pipe0 {
label = "ssusb-qdss-in-0";
qcom,usb-bam-mem-type = <2>;
qcom,dir = <1>;
qcom,pipe-num = <0>;
qcom,peer-bam = <0>;
qcom,peer-bam-physical-address = <0x10064000>;
qcom,src-bam-pipe-index = <0>;
qcom,dst-bam-pipe-index = <0>;
qcom,data-fifo-offset = <0x0>;
qcom,data-fifo-size = <0x1800>;
qcom,descriptor-fifo-offset = <0x1800>;
qcom,descriptor-fifo-size = <0x800>;
};
};
};
/* USB port related High Speed PHY */
usb2_phy0: hsphy@88e3000 {
compatible = "qcom,usb-hsphy-snps-femto";
reg = <0x88e3000 0x114>,
<0x088e2000 0x4>;
reg-names = "hsusb_phy_base",
"eud_enable_reg";
vdd-supply = <&pm8350_l5>;
vdda18-supply = <&pm8350c_l1>;
vdda33-supply = <&pm8350_l2>;
qcom,vdd-voltage-level = <0 880000 880000>;
clocks = <&clock_rpmh RPMH_CXO_CLK>;
clock-names = "ref_clk_src";
resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;
reset-names = "phy_reset";
};
/* USB port related QMP USB DP Combo PHY */
usb_qmp_dp_phy: ssphy@88e8000 {
compatible = "qcom,usb-ssphy-qmp-dp-combo";
reg = <0x88e8000 0x3000>;
reg-names = "qmp_phy_base";
vdd-supply = <&pm8350_l1>;
qcom,vdd-voltage-level = <0 912000 912000>;
qcom,vdd-max-load-uA = <47000>;
core-supply = <&pm8350_l6>;
clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
<&clock_gcc USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK>,
<&clock_rpmh RPMH_CXO_CLK>,
<&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
"pipe_clk_ext_src", "ref_clk_src",
"com_aux_clk";
resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&clock_gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "global_phy_reset", "phy_reset";
pinctrl-names = "default";
pinctrl-0 = <&usb3phy_portselect_default>;
qcom,qmp-phy-reg-offset =
<USB3_DP_PCS_PCS_STATUS1
USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
USB3_DP_PCS_POWER_DOWN_CONTROL
USB3_DP_PCS_SW_RESET
USB3_DP_PCS_START_CONTROL
0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
USB3_DP_COM_POWER_DOWN_CTRL
USB3_DP_COM_SW_RESET
USB3_DP_COM_RESET_OVRD_CTRL
USB3_DP_COM_PHY_MODE_CTRL
USB3_DP_COM_TYPEC_CTRL
USB3_DP_PCS_CLAMP_ENABLE>;
qcom,qmp-phy-init-seq =
/* <reg_offset, value, delay> */
<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0
USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0
USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0
USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E 0
USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35 0
USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F 0
USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F 0
USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F 0
USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21 0
USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x0A 0
USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x03 0
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0
USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F 0
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB 0
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B 0
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB 0
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D 0
USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB 0
USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64 0
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24 0
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2 0
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13 0
USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9 0
USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
USB3_DP_QSERDES_RXA_GM_CAL 0x00 0
USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0
USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0
USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0
USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E 0
USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35 0
USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F 0
USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F 0
USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0
USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21 0
USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x0A 0
USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x03 0
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0
USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F 0
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB 0
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B 0
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB 0
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C 0
USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB 0
USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64 0
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24 0
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2 0
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13 0
USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9 0
USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
USB3_DP_QSERDES_RXB_GM_CAL 0x00 0
USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 0
USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00 0
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0
USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0
USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0
USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
USB3_DP_PCS_RX_SIGDET_LVL 0xAA 0
USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
USB3_DP_PCS_EQ_CONFIG1 0x4B 0
USB3_DP_PCS_EQ_CONFIG5 0x10 0
USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
0xffffffff 0xffffffff 0x00>;
};
usb_audio_qmi_dev {
compatible = "qcom,usb-audio-qmi-dev";
iommus = <&apps_smmu 0x180f 0x0>;
qcom,iommu-dma = "disabled";
qcom,usb-audio-stream-id = <0xf>;
qcom,usb-audio-intr-num = <2>;
};
};

11
qcom/waipio-v2-atp-pm8008.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio-v2.dtsi"
#include "waipio-atp.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio v2 ATP with PM8008";
compatible = "qcom,waipio-atp", "qcom,waipio", "qcom,atp";
qcom,board-id = <33 0>;
};

11
qcom/waipio-v2-atp-pm8010.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio-v2.dtsi"
#include "waipio-atp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio v2 ATP with PM8010";
compatible = "qcom,waipio-atp", "qcom,waipio", "qcom,atp";
qcom,board-id = <0x10021 0>;
};

11
qcom/waipio-v2-cdp-pm8008.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio-v2.dtsi"
#include "waipio-cdp.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio v2 CDP with PM8008";
compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
qcom,board-id = <1 0>;
};

11
qcom/waipio-v2-cdp-pm8010.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio-v2.dtsi"
#include "waipio-cdp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio v2 CDP with PM8010";
compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
qcom,board-id = <0x10001 0>;
};

95
qcom/waipio-v2-gpu.dtsi Normal file
View File

@@ -0,0 +1,95 @@
&msm_gpu {
compatible = "qcom,adreno-gpu-c500v2", "qcom,kgsl-3d0";
qcom,initial-pwrlevel = <7>;
qcom,gpu-model = "Adreno730v2";
qcom,gpu-pwrlevels {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels";
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <734000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
qcom,bus-freq = <10>;
qcom,bus-min = <9>;
qcom,bus-max = <10>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <640000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
qcom,bus-freq = <10>;
qcom,bus-min = <6>;
qcom,bus-max = <10>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <599000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
qcom,bus-freq = <8>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <545000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq = <8>;
qcom,bus-min = <6>;
qcom,bus-max = <9>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <492000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
qcom,bus-freq = <6>;
qcom,bus-min = <6>;
qcom,bus-max = <8>;
};
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <421000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq = <6>;
qcom,bus-min = <3>;
qcom,bus-max = <8>;
};
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <350000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
qcom,bus-freq = <3>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
};
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <285000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
qcom,bus-freq = <2>;
qcom,bus-min = <1>;
qcom,bus-max = <5>;
};
};
};

11
qcom/waipio-v2-mtp-pm8008.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio-v2.dtsi"
#include "waipio-mtp.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio v2 MTP with PM8008";
compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
qcom,board-id = <8 0>;
};

11
qcom/waipio-v2-mtp-pm8010.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio-v2.dtsi"
#include "waipio-mtp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio v2 MTP with PM8010";
compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
qcom,board-id = <0x10008 0>;
};

11
qcom/waipio-v2-qrd-pm8008.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio-v2.dtsi"
#include "waipio-qrd.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio v2 QRD with PM8008";
compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
qcom,board-id = <11 0>;
};

11
qcom/waipio-v2-qrd-pm8010-2s.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio-v2.dtsi"
#include "waipio-qrd-2s.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio v2 QRD with PM8010 + 2S";
compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
qcom,board-id = <0x2000b 0>;
};

11
qcom/waipio-v2-qrd-pm8010.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipio-v2.dtsi"
#include "waipio-qrd.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio v2 QRD with PM8010";
compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
qcom,board-id = <0x1000b 0>;
};

9
qcom/waipio-v2.dts Normal file
View File

@@ -0,0 +1,9 @@
/dts-v1/;
#include "waipio-v2.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio v2 SoC";
compatible = "qcom,waipio";
qcom,board-id = <0 0>;
};

185
qcom/waipio-v2.dtsi Normal file
View File

@@ -0,0 +1,185 @@
#include "waipio.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio v2";
compatible = "qcom,waipio";
qcom,msm-id = <457 0x20000>;
};
&CPU4 {
dynamic-power-coefficient = <259>;
};
&CPU5 {
dynamic-power-coefficient = <259>;
};
&CPU6 {
dynamic-power-coefficient = <259>;
};
&CPU7 {
dynamic-power-coefficient = <450>;
};
&clock_camcc {
compatible = "qcom,waipio-camcc-v2", "syscon";
};
&clock_gpucc {
compatible = "qcom,waipio-gpucc-v2", "syscon";
};
&qcom_memlat {
ddr {
silver {
qcom,cpufreq-memfreq-tbl =
< 300000 200000 >,
< 614400 451000 >,
< 1171200 547000 >,
< 1478400 768000 >,
< 1785600 1555000 >;
};
gold {
qcom,cpufreq-memfreq-tbl =
< 300000 200000 >,
< 633600 451000 >,
< 883200 547000 >,
< 1113600 768000 >,
< 1324800 1555000 >,
< 1881600 2092000 >,
< 2630400 2736000 >,
< 2995200 3196000 >;
};
gold-compute {
qcom,cpufreq-memfreq-tbl =
< 1881600 200000 >,
< 2995200 1555000 >;
};
prime-latfloor {
qcom,cpufreq-memfreq-tbl =
< 2630400 200000 >,
< 2995200 3196000 >;
};
};
llcc {
silver {
qcom,cpufreq-memfreq-tbl =
< 300000 150000 >,
< 614400 300000 >,
< 1478400 466000 >,
< 1785600 600000 >;
};
gold {
qcom,cpufreq-memfreq-tbl =
< 300000 150000 >,
< 633600 300000 >,
< 1113600 466000 >,
< 1324800 600000 >,
< 1881600 806000 >,
< 2630400 933000 >,
< 2995200 1066000 >;
};
gold-compute {
qcom,cpufreq-memfreq-tbl =
< 1881600 150000 >,
< 2995200 600000 >;
};
};
l3 {
silver {
qcom,cpufreq-memfreq-tbl =
< 300000 307200 >,
< 403200 422400 >,
< 614400 537600 >,
< 729600 633600 >,
< 844800 729600 >,
< 960000 825600 >,
< 1075200 998400 >,
< 1267200 1094400 >,
< 1363200 1267200 >,
< 1478400 1459200 >,
< 1574400 1555200 >,
< 1785600 1651200 >;
};
silver-latboost {
qcom,cpufreq-memfreq-tbl =
< 300000 307200 >,
< 403200 729600 >,
< 614400 825600 >,
< 729600 998400 >,
< 844800 1094400 >,
< 960000 1267200 >,
< 1075200 1459200 >,
< 1267200 1555200 >,
< 1785600 1651200 >;
};
gold {
qcom,cpufreq-memfreq-tbl =
< 300000 307200 >,
< 633600 537600 >,
< 883200 633600 >,
< 1113600 825600 >,
< 1324800 998400 >,
< 1651200 1267200 >,
< 1996800 1459200 >,
< 2496000 1555200 >,
< 2995200 1651200 >;
};
gold-latboost {
qcom,cpufreq-memfreq-tbl =
< 300000 307200 >,
< 633600 998400 >,
< 883200 1267200 >,
< 1113600 1459200 >,
< 1324800 1555200 >,
< 2995200 1651200 >;
};
prime {
qcom,cpufreq-memfreq-tbl =
< 300000 307200 >,
< 633600 537600 >,
< 883200 633600 >,
< 1113600 825600 >,
< 1324800 998400 >,
< 1651200 1267200 >,
< 1996800 1459200 >,
< 2496000 1555200 >,
< 2995200 1651200 >;
};
prime-compute {
qcom,cpufreq-memfreq-tbl =
< 2054400 307200 >,
< 2995200 1651200 >;
};
};
ddrqos {
gold {
qcom,cpufreq-memfreq-tbl =
< 1881600 0 >,
< 2995200 1 >;
};
prime-latfloor {
qcom,cpufreq-memfreq-tbl =
< 2054400 0 >,
< 2995200 1 >;
};
};
};
#include "waipio-v2-gpu.dtsi"

10
qcom/waipio-vm-cdp.dts Normal file
View File

@@ -0,0 +1,10 @@
/dts-v1/;
#include "waipio-vm.dtsi"
#include "waipio-vm-cdp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio SVM CDP";
compatible = "qcom,waipio-cdp", "qcom,waipio", "qcom,cdp";
qcom,board-id = <0x10001 0>;
};

15
qcom/waipio-vm-cdp.dtsi Normal file
View File

@@ -0,0 +1,15 @@
&qupv3_se4_i2c {
status = "ok";
focaltech@38 {
compatible = "focaltech,fts_ts";
reg = <0x38>;
focaltech,display-coords = <0 0 1080 2340>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "tvm";
focaltech,trusted-touch-spi-irq = <754>;
focaltech,trusted-touch-io-bases = <0xF110000 0xF111000 0xF112000 0xF113000
0xF114000 0xF115000 0x990000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000
0x1000 0x1000 0x1000 0x4000>;
};
};

13
qcom/waipio-vm-dma-heaps.dtsi Normal file
View File

@@ -0,0 +1,13 @@
#include <dt-bindings/arm/msm/qcom_dma_heap_dt_constants.h>
&soc {
qcom,dma-heaps {
compatible = "qcom,dma-heaps";
qcom,tui {
qcom,dma-heap-name = "qcom,tui";
qcom,dma-heap-type = <HEAP_TYPE_CARVEOUT>;
qcom,dynamic-heap;
};
};
};

10
qcom/waipio-vm-mtp.dts Normal file
View File

@@ -0,0 +1,10 @@
/dts-v1/;
#include "waipio-vm.dtsi"
#include "waipio-vm-mtp.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio SVM MTP";
compatible = "qcom,waipio-mtp", "qcom,waipio", "qcom,mtp";
qcom,board-id = <0x10008 0>;
};

16
qcom/waipio-vm-mtp.dtsi Normal file
View File

@@ -0,0 +1,16 @@
&qupv3_se4_i2c {
status = "ok";
focaltech@38 {
compatible = "focaltech,fts_ts";
reg = <0x38>;
focaltech,display-coords = <0 0 1080 2340>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "tvm";
focaltech,trusted-touch-spi-irq = <754>;
focaltech,trusted-touch-io-bases = <0xF110000 0xF111000 0xF112000 0xF113000
0xF114000 0xF115000 0x990000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000
0x1000 0x1000 0x1000 0x4000>;
};
};

10
qcom/waipio-vm-qrd.dts Normal file
View File

@@ -0,0 +1,10 @@
/dts-v1/;
#include "waipio-vm.dtsi"
#include "waipio-vm-qrd.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio SVM QRD";
compatible = "qcom,waipio-qrd", "qcom,waipio", "qcom,qrd";
qcom,board-id = <0x1000B 0>;
};

26
qcom/waipio-vm-qrd.dtsi Normal file
View File

@@ -0,0 +1,26 @@
&soc {
};
&qupv3_se4_i2c {
status = "disabled";
};
&qupv3_se4_spi {
status = "ok";
qcom,spi-touch-active = "focaltech,fts_ts";
focaltech@0 {
compatible = "focaltech,fts_ts";
reg = <0x0>;
spi-max-frequency = <6000000>;
focaltech,max-touch-number = <5>;
focaltech,display-coords = <0 0 1080 2340>;
focaltech,ic-type = <0x3658D488>;
focaltech,trusted-touch-mode = "vm_mode";
focaltech,touch-environment = "tvm";
focaltech,trusted-touch-spi-irq = <754>;
focaltech,trusted-touch-io-bases = <0xF110000 0xF111000 0xF112000 0xF113000 0xF114000 0xF115000 0x990000 0x00910000>;
focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>;
};
};

10
qcom/waipio-vm-rumi.dts Normal file
View File

@@ -0,0 +1,10 @@
/dts-v1/;
#include "waipio-vm.dtsi"
#include "waipio-vm-rumi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio SVM RUMI";
compatible = "qcom,waipio-rumi", "qcom,waipio", "qcom,rumi";
qcom,board-id = <15 0>;
};

3
qcom/waipio-vm-rumi.dtsi Normal file
View File

@@ -0,0 +1,3 @@
&arch_timer {
clock-frequency = <500000>;
};

374
qcom/waipio-vm.dtsi Normal file
View File

@@ -0,0 +1,374 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-waipio.h>
#include <dt-bindings/clock/qcom,rpmh.h>
/ {
#address-cells = <0x2>;
#size-cells = <0x2>;
qcom,msm-id = <457 0x10000>;
interrupt-parent = <&vgic>;
qcom,mem-buf {
compatible = "qcom,mem-buf";
qcom,mem-buf-capabilities = "consumer";
qcom,vmid = <45>;
};
qcom,mem-buf-msgq {
compatible = "qcom,mem-buf-msgq";
};
chosen {
bootargs = "nokaslr log_buf_len=256K root=/dev/ram rw init=/init console=hvc0 loglevel=8";
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
system_cma: linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x400000>;
linux,cma-default;
};
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
CPU0: cpu@0 {
compatible = "arm,armv8";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
cpu-idle-states = <&CPU_PWR_DWN
&CLUSTER_PWR_DWN>;
};
CPU1: cpu@100 {
compatible = "arm,armv8";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
cpu-idle-states = <&CPU_PWR_DWN
&CLUSTER_PWR_DWN>;
};
};
idle-states {
CPU_PWR_DWN: c4 { /* Using Gold C4 latencies */
compatible = "arm,idle-state";
idle-state-name = "rail-pc";
entry-latency-us = <369>;
exit-latency-us = <1502>;
min-residency-us = <4488>;
arm,psci-suspend-param = <0x40000004>;
local-timer-stop;
};
CLUSTER_PWR_DWN: d4 { /* C4+D4 */
compatible = "arm,idle-state";
idle-state-name = "l3-pc";
entry-latency-us = <584>;
exit-latency-us = <2332>;
min-residency-us = <6118>;
arm,psci-suspend-param = <0x40000044>;
local-timer-stop;
};
};
qrtr-gunyah {
compatible = "qcom,qrtr-gunyah";
gunyah-label = <3>;
};
qcom,vm-config {
compatible = "qcom,vm-1.0";
vm-type = "aarch64-guest";
boot-config = "fdt,unified";
os-type = "linux";
kernel-entry-segment = "kernel";
kernel-entry-offset = <0x0 0x0>;
vendor = "Qualcomm";
image-name = "qcom,trustedvm";
qcom,pasid = <0x0 0x1c>;
iomemory-ranges = <0x0 0x92c000 0x0 0x92c000 0x0 0x4000 0x0
0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1
0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1
0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1
0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1
0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>;
gic-irq-ranges = <283 283>; /* PVM->SVM IRQ transfer */
memory {
#address-cells = <0x2>;
#size-cells = <0x0>;
base-address = <0x0 0xe0b00000>;
size-min = <0x0 0x7a00000>; /* 122 MB */
};
segments {
ramdisk = <2>; /* 8MB */
};
vcpus {
config = "/cpus";
affinity = "static";
affinity-map = <0x5 0x6>;
sched-priority = <0>; /* relative to PVM */
sched-timeslice = <2000>; /* in ms */
};
interrupts {
config = &vgic;
};
vdevices {
generate = "/hypervisor";
rm-rpc {
vdevice-type = "rm-rpc";
generate = "/hypervisor/qcom,resource-mgr";
console-dev;
message-size = <0x000000f0>;
queue-depth = <0x00000008>;
qcom,label = <0x1>;
};
virtio-mmio@0 {
vdevice-type = "virtio-mmio";
generate = "/virtio-mmio";
peer-default;
vqs-num = <0x1>;
push-compatible = "virtio,mmio";
dma-coherent;
dma_base = <0x0 0x0>;
memory {
qcom,label = <0x11>;
#address-cells = <0x2>;
base = <0x0 0xFFEFC000>;
};
};
swiotlb-shm {
vdevice-type = "shm";
generate = "/swiotlb";
push-compatible = "swiotlb";
peer-default;
dma_base = <0x0 0x4000>;
memory {
qcom,label = <0x12>;
#address-cells = <0x2>;
base = <0x0 0xFFF00000>;
};
};
mem-buf-message-queue-pair {
vdevice-type = "message-queue-pair";
generate = "/hypervisor/membuf-msgq-pair";
message-size = <0x000000f0>;
queue-depth = <0x00000008>;
peer-default;
qcom,label = <0x0000001>;
};
display-message-queue-pair {
vdevice-type = "message-queue-pair";
generate = "/hypervisor/display-msgq-pair";
message-size = <0x000000f0>;
queue-depth = <0x00000008>;
peer-default;
qcom,label = <0x0000002>;
};
qrtr-shm {
vdevice-type = "shm-doorbell";
generate = "/hypervisor/qrtr-shm";
push-compatible = "qcom,qrtr-gunyah-gen";
peer-default;
memory {
qcom,label = <0x3>;
allocate-base;
};
};
gpiomem0 {
vdevice-type = "iomem";
patch = "/soc/tlmm-vm-mem-access";
push-compatible = "qcom,tlmm-vm-mem-access";
peer-default;
memory {
qcom,label = <0x8>;
qcom,mem-info-tag = <0x2>;
allocate-base;
};
};
};
};
firmware: firmware {
scm {
compatible = "qcom,scm";
};
};
soc: soc { };
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
spmi_bus: qcom,spmi@c42d000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc42d000 0x4000>,
<0xc400000 0x3000>,
<0xc500000 0x400000>,
<0xc440000 0x80000>,
<0xc4c0000 0x10000>;
reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
#address-cells = <2>;
#size-cells = <0>;
cell-index = <0>;
qcom,channel = <0>;
qcom,ee = <0>;
qcom,bus-id = <0>;
};
vm_tlmm_irq: vm-tlmm-irq@0 {
compatible = "qcom,tlmm-vm-irq";
reg = <0x0 0x0>;
interrupt-controller;
#interrupt-cells = <2>;
};
tlmm: pinctrl@f000000 {
compatible = "qcom,waipio-vm-pinctrl";
reg = <0x0F000000 0x1000000>;
interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
/* Valid pins */
gpios = /bits/ 16 <64 65 66 67 0 4 86 87>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
tlmm-vm-mem-access {
compatible = "qcom,tlmm-vm-mem-access";
tlmm-vm-gpio-list = <365 366 367 368 301 305 387 388>;
};
vgic: interrupt-controller@17100000 {
compatible = "arm,gic-v3";
interrupt-controller;
#interrupt-cells = <0x3>;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x40000>;
reg = <0x17100000 0x10000>, /* GICD */
<0x17180000 0x100000>; /* GICR * 8 */
};
arch_timer: timer {
compatible = "arm,armv8-timer";
always-on;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
/*
* QUPv3 Instances
* North 4 : SE 4
*/
/* QUPv3_0 wrapper instance: North QUP */
qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
compatible = "qcom,qupv3-geni-se";
reg = <0x9c0000 0x2000>;
status = "ok";
};
/* GPI */
gpi_dma0: qcom,gpi-dma@900000 {
compatible = "qcom,gpi-dma";
#dma-cells = <5>;
reg = <0x900000 0x60000>;
reg-names = "gpi-top";
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
qcom,max-num-gpii = <12>;
qcom,gpii-mask = <0x80>;
qcom,ev-factor = <2>;
qcom,gpi-ee-offset = <0x10000>;
qcom,le-vm;
status = "ok";
};
/* I2C SE */
qupv3_se4_i2c: i2c@990000 {
compatible = "qcom,i2c-geni";
reg = <0x990000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&gpi_dma0 0 4 3 64 0>,
<&gpi_dma0 1 4 3 64 0>;
dma-names = "tx", "rx";
qcom,wrapper-core = <&qupv3_0>;
qcom,le-vm;
status = "disabled";
};
qupv3_se4_spi: spi@990000 {
compatible = "qcom,spi-geni";
reg = <0x990000 0x4000>;
reg-names = "se_phys";
#address-cells = <1>;
#size-cells = <0>;
dmas = <&gpi_dma0 0 4 1 64 0>,
<&gpi_dma0 1 4 1 64 0>;
dma-names = "tx", "rx";
spi-max-frequency = <50000000>;
qcom,wrapper-core = <&qupv3_0>;
qcom,le-vm;
status = "disabled";
};
qcom_smcinvoke {
compatible = "qcom,smcinvoke";
};
qtee_shmbridge {
compatible = "qcom,tee-shared-memory-bridge";
qcom,custom-bridge-size = <512>;
qcom,support-hypervisor;
};
};
#include "waipio-vm-dma-heaps.dtsi"
#include "msm-arm-smmu-waipio-vm.dtsi"

9
qcom/waipio.dts Normal file
View File

@@ -0,0 +1,9 @@
/dts-v1/;
#include "waipio.dtsi"
/ {
model = "Qualcomm Technologies, Inc. Waipio SoC";
compatible = "qcom,waipio";
qcom,board-id = <0 0>;
};

3661
qcom/waipio.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

11
qcom/waipiop-cdp-pm8008.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipiop.dtsi"
#include "waipio-cdp.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. WaipioP CDP with PM8008";
compatible = "qcom,waipiop-cdp", "qcom,waipiop", "qcom,cdp";
qcom,board-id = <1 0>;
};

11
qcom/waipiop-cdp-pm8010.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipiop.dtsi"
#include "waipio-cdp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. WaipioP CDP with PM8010";
compatible = "qcom,waipiop-cdp", "qcom,waipiop", "qcom,cdp";
qcom,board-id = <0x10001 0>;
};

12
qcom/waipiop-hdk-pm8010-overlay.dts Normal file
View File

@@ -0,0 +1,12 @@
/dts-v1/;
/plugin/;
#include "waipio-hdk.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. WaipioP HDK with PM8010";
compatible = "qcom,waipiop-hdk", "qcom,waipiop", "qcom,hdk";
qcom,msm-id = <482 0x10000>, <482 0x20000>;
qcom,board-id = <0x1001f 0>;
};

11
qcom/waipiop-hdk-pm8010.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipiop.dtsi"
#include "waipio-hdk.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. WaipioP HDK with PM8010";
compatible = "qcom,waipiop-hdk", "qcom,waipiop", "qcom,hdk";
qcom,board-id = <0x1001f 0>;
};

11
qcom/waipiop-mtp-pm8008.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipiop.dtsi"
#include "waipio-mtp.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. WaipioP MTP with PM8008";
compatible = "qcom,waipiop-mtp", "qcom,waipiop", "qcom,mtp";
qcom,board-id = <8 0>;
};

11
qcom/waipiop-mtp-pm8010.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipiop.dtsi"
#include "waipio-mtp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. WaipioP MTP with PM8010";
compatible = "qcom,waipiop-mtp", "qcom,waipiop", "qcom,mtp";
qcom,board-id = <0x10008 0>;
};

11
qcom/waipiop-qrd-pm8008.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipiop.dtsi"
#include "waipio-qrd.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. WaipioP QRD with PM8008";
compatible = "qcom,waipiop-qrd", "qcom,waipiop", "qcom,qrd";
qcom,board-id = <11 0>;
};

11
qcom/waipiop-qrd-pm8010-2s.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipiop.dtsi"
#include "waipio-qrd-2s.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. WaipioP QRD with PM8010";
compatible = "qcom,waipiop-qrd", "qcom,waipiop", "qcom,qrd";
qcom,board-id = <0x2000b 0>;
};

11
qcom/waipiop-qrd-pm8010.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipiop.dtsi"
#include "waipio-qrd.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. WaipioP QRD with PM8010";
compatible = "qcom,waipiop-qrd", "qcom,waipiop", "qcom,qrd";
qcom,board-id = <0x1000b 0>;
};

11
qcom/waipiop-v2-cdp-pm8008.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipiop-v2.dtsi"
#include "waipio-cdp.dtsi"
#include "waipio-pm8008.dtsi"
/ {
model = "Qualcomm Technologies, Inc. WaipioP v2 CDP with PM8008";
compatible = "qcom,waipiop-cdp", "qcom,waipiop", "qcom,cdp";
qcom,board-id = <1 0>;
};

11
qcom/waipiop-v2-cdp-pm8010.dts Normal file
View File

@@ -0,0 +1,11 @@
/dts-v1/;
#include "waipiop-v2.dtsi"
#include "waipio-cdp.dtsi"
#include "waipio-pm8010-spmi.dtsi"
/ {
model = "Qualcomm Technologies, Inc. WaipioP v2 CDP with PM8010";
compatible = "qcom,waipiop-cdp", "qcom,waipiop", "qcom,cdp";
qcom,board-id = <0x10001 0>;
};

Some files were not shown because too many files have changed in this diff Show More