Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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ARM: dts: msm: Make PCIe0 to enumerate with x2 lane for sdxpinn

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Some sdxpinn targets have fuse blown parts and so in those targets
one PCIe lane got disabled for PCIe0 and such devices are
enumerates with x1 lane width.

Hence, updated in PHY settings for PCIe0 to make sure that device
enumerate with x2 lane width for PCIe0 of all sdxpinn targets.

Change-Id: I2fdac831e670c2573541cb2e53a8c0f252f7f6e5
This commit is contained in:
Jyothi Kumar Seerapu
2022-11-08 20:05:52 +05:30
committed by Gerrit - the friendly Code Review server
parent 2d3606f3aa
commit 1ac8836230
1 changed files with 1 additions and 1 deletions
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qcom/sdxpinn-pcie.dtsi
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