Jyothi Kumar Seerapu 1ac8836230 ARM: dts: msm: Make PCIe0 to enumerate with x2 lane for sdxpinn
Some sdxpinn targets have fuse blown parts and so in those targets
one PCIe lane got disabled for PCIe0 and such devices are
enumerates with x1 lane width.

Hence, updated in PHY settings for PCIe0 to make sure that device
enumerate with x2 lane width for PCIe0 of all sdxpinn targets.

Change-Id: I2fdac831e670c2573541cb2e53a8c0f252f7f6e5
2022-11-21 02:06:09 -08:00
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