mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
ARM: dts: msm: Add QUPv3 node for SA410M target
Add I2C/SPI/UART QUPv3 node for SA410M target. Change-Id: Id7e4e6690b4eccd25e1a903d9dc7154f04fdb2a1
This commit is contained in:
Aniket Randive
@@ -1,4 +1,440 @@
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&tlmm {
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qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
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qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active {
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mux {
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pins = "gpio0";
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function = "qup0_se0_l0";
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};
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config {
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pins = "gpio0";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active {
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mux {
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pins = "gpio1";
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function = "qup0_se0_l1";
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};
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config {
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pins = "gpio1";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
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mux {
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pins = "gpio0", "gpio1";
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function = "gpio";
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};
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config {
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pins = "gpio0", "gpio1";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se0_spi_pins: qupv3_se0_spi_pins {
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qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active {
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mux {
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pins = "gpio0";
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function = "qup0_se0_l0";
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};
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config {
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pins = "gpio0";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active {
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mux {
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pins = "gpio1";
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function = "qup0_se0_l1";
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};
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config {
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pins = "gpio1";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active {
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mux {
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pins = "gpio2";
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function = "qup0_se0_l2";
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};
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config {
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pins = "gpio2";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active {
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mux {
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pins = "gpio3";
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function = "qup0_se0_l3";
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};
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config {
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pins = "gpio3";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
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mux {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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function = "gpio";
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};
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config {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
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qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active {
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mux {
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pins = "gpio4";
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function = "qup0_se1_l0";
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};
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config {
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pins = "gpio4";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active {
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mux {
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pins = "gpio5";
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function = "qup0_se1_l1";
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};
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config {
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pins = "gpio5";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
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mux {
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pins = "gpio4", "gpio5";
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function = "gpio";
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};
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config {
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pins = "gpio4", "gpio5";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se1_spi_pins: qupv3_se1_spi_pins {
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qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active {
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mux {
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pins = "gpio4";
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function = "qup0_se1_l0";
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};
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config {
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pins = "gpio4";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active {
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mux {
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pins = "gpio5";
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function = "qup0_se1_l1";
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};
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config {
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pins = "gpio5";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active {
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mux {
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pins = "gpio69";
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function = "qup0_se1_l2";
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};
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config {
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pins = "gpio69";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active {
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mux {
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pins = "gpio70";
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function = "qup0_se1_l3";
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};
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config {
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pins = "gpio70";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
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mux {
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pins = "gpio4", "gpio5",
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"gpio69", "gpio70";
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function = "gpio";
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};
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config {
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pins = "gpio4", "gpio5",
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"gpio69", "gpio70";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
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qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active {
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mux {
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pins = "gpio6";
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function = "qup0_se2_l0";
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};
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config {
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pins = "gpio6";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active {
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mux {
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pins = "gpio7";
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function = "qup0_se2_l1";
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};
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config {
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pins = "gpio7";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
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mux {
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pins = "gpio6", "gpio7";
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function = "gpio";
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};
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config {
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pins = "gpio6", "gpio7";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se2_spi_pins: qupv3_se2_spi_pins {
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qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active {
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mux {
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pins = "gpio6";
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function = "qup0_se2_l0";
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};
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config {
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pins = "gpio6";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active {
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mux {
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pins = "gpio7";
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function = "qup0_se2_l1";
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};
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config {
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pins = "gpio7";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active {
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mux {
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pins = "gpio71";
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function = "qup0_se2_l2";
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};
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config {
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pins = "gpio71";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active {
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mux {
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pins = "gpio80";
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function = "qup0_se2_l3";
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};
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config {
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pins = "gpio80";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
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mux {
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pins = "gpio6", "gpio7",
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"gpio71", "gpio80";
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function = "gpio";
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};
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config {
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pins = "gpio6", "gpio7",
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"gpio71", "gpio80";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se3_4uart_pins: qupv3_se3_4uart_pins {
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qupv3_se3_default_cts: qupv3_se3_default_cts {
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mux {
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pins = "gpio8";
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function = "gpio";
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};
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config {
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pins = "gpio8";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se3_default_rts: qupv3_se3_default_rts {
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mux {
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pins = "gpio9";
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function = "gpio";
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};
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config {
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pins = "gpio9";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se3_default_tx: qupv3_se3_default_tx {
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mux {
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pins = "gpio10";
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function = "gpio";
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};
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config {
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pins = "gpio10";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se3_default_rx: qupv3_se3_default_rx {
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mux {
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pins = "gpio11";
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function = "gpio";
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};
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config {
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pins = "gpio11";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se3_cts: qupv3_se3_cts {
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mux {
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pins = "gpio8";
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function = "qup0_se3_l0";
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};
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config {
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pins = "gpio8";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se3_rts: qupv3_se3_rts {
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mux {
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pins = "gpio9";
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function = "qup0_se3_l1";
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};
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config {
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pins = "gpio9";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se3_tx: qupv3_se3_tx {
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mux {
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pins = "gpio10";
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function = "qup0_se3_l2";
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};
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config {
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pins = "gpio10";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se3_rx: qupv3_se3_rx {
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mux {
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pins = "gpio11";
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function = "qup0_se3_l3";
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};
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config {
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pins = "gpio11";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se4_2uart_pins: qupv3_se4_2uart_pins {
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qupv3_se4_2uart_tx_active: qupv3_se4_2uart_tx_active {
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mux {
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@@ -39,4 +475,114 @@
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};
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};
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};
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qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
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qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active {
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mux {
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pins = "gpio14";
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function = "qup0_se5_l0";
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};
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config {
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pins = "gpio14";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active {
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mux {
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pins = "gpio15";
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function = "qup0_se5_l1";
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};
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config {
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pins = "gpio15";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
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mux {
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pins = "gpio14", "gpio15";
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function = "gpio";
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};
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config {
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pins = "gpio14", "gpio15";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se5_spi_pins: qupv3_se5_spi_pins {
|
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qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio14";
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function = "qup0_se5_l0";
|
||||
};
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config {
|
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pins = "gpio14";
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drive-strength = <6>;
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bias-disable;
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};
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||||
};
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qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active {
|
||||
mux {
|
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pins = "gpio15";
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function = "qup0_se5_l1";
|
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};
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config {
|
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pins = "gpio15";
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drive-strength = <6>;
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bias-disable;
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||||
};
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};
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qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active {
|
||||
mux {
|
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pins = "gpio16";
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function = "qup0_se5_l2";
|
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};
|
||||
|
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config {
|
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pins = "gpio16";
|
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drive-strength = <6>;
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bias-disable;
|
||||
};
|
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};
|
||||
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qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active {
|
||||
mux {
|
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pins = "gpio17";
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function = "qup0_se5_l3";
|
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};
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||||
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config {
|
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pins = "gpio17";
|
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drive-strength = <6>;
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bias-disable;
|
||||
};
|
||||
};
|
||||
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qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
|
||||
mux {
|
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pins = "gpio14", "gpio15",
|
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"gpio16", "gpio17";
|
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function = "gpio";
|
||||
};
|
||||
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config {
|
||||
pins = "gpio14", "gpio15",
|
||||
"gpio16", "gpio17";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -1,4 +1,30 @@
|
||||
&soc {
|
||||
/* GPI Instance */
|
||||
gpi_dma0: qcom,gpi-dma@4a00000 {
|
||||
compatible = "qcom,gpi-dma";
|
||||
#dma-cells = <5>;
|
||||
reg = <0x4a00000 0x60000>;
|
||||
reg-names = "gpi-top";
|
||||
iommus = <&apps_smmu 0xf6 0x0>;
|
||||
qcom,max-num-gpii = <10>;
|
||||
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,gpii-mask = <0x3ff>;
|
||||
qcom,ev-factor = <2>;
|
||||
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
|
||||
qcom,gpi-ee-offset = <0x10000>;
|
||||
dma-coherent;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
/* QUPv3_0 wrapper instance */
|
||||
qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
|
||||
compatible = "qcom,geni-se-qup";
|
||||
@@ -33,5 +59,243 @@
|
||||
pinctrl-1 = <&qupv3_se4_2uart_sleep>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se0_i2c: i2c@4a80000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a80000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se0_i2c_sda_active>, <&qupv3_se0_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 0 3 64 0>,
|
||||
<&gpi_dma0 1 0 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se0_spi: spi@4a80000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a80000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se0_spi_mosi_active>, <&qupv3_se0_spi_miso_active>,
|
||||
<&qupv3_se0_spi_clk_active>, <&qupv3_se0_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se0_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 0 1 64 0>,
|
||||
<&gpi_dma0 1 0 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se0_4uart: qcom,qup_uart@4a80000 {
|
||||
compatible = "qcom,msm-geni-serial-hs";
|
||||
reg = <0x4a80000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "active", "sleep", "shutdown";
|
||||
pinctrl-0 = <&qupv3_se0_default_cts>, <&qupv3_se0_default_rts>,
|
||||
<&qupv3_se0_default_tx>, <&qupv3_se0_default_rx>;
|
||||
pinctrl-1 = <&qupv3_se0_cts>, <&qupv3_se0_rts>,
|
||||
<&qupv3_se0_tx>, <&qupv3_se0_rx>;
|
||||
pinctrl-2 = <&qupv3_se0_cts>, <&qupv3_se0_rts>,
|
||||
<&qupv3_se0_tx>, <&qupv3_se0_default_rx>;
|
||||
pinctrl-3 = <&qupv3_se0_default_cts>, <&qupv3_se0_default_rts>,
|
||||
<&qupv3_se0_default_tx>, <&qupv3_se0_default_rx>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se1_i2c: i2c@4a84000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a84000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_i2c_sda_active>, <&qupv3_se1_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 1 3 64 0>,
|
||||
<&gpi_dma0 1 1 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se1_spi: spi@4a84000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a84000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_spi_mosi_active>, <&qupv3_se1_spi_miso_active>,
|
||||
<&qupv3_se1_spi_clk_active>, <&qupv3_se1_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se1_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 1 1 64 0>,
|
||||
<&gpi_dma0 1 1 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se2_i2c: i2c@4a88000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a88000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se2_i2c_sda_active>, <&qupv3_se2_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 2 3 64 0>,
|
||||
<&gpi_dma0 1 2 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se2_spi: spi@4a88000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a88000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se2_spi_mosi_active>, <&qupv3_se2_spi_miso_active>,
|
||||
<&qupv3_se2_spi_clk_active>, <&qupv3_se2_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se2_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 2 1 64 0>,
|
||||
<&gpi_dma0 1 2 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* HS UART Instance */
|
||||
qupv3_se3_4uart: qcom,qup_uart@4a8c000 {
|
||||
compatible = "qcom,msm-geni-serial-hs";
|
||||
reg = <0x4a8c000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "active", "sleep", "shutdown";
|
||||
pinctrl-0 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>,
|
||||
<&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>;
|
||||
pinctrl-1 = <&qupv3_se3_cts>, <&qupv3_se3_rts>,
|
||||
<&qupv3_se3_tx>, <&qupv3_se3_rx>;
|
||||
pinctrl-2 = <&qupv3_se3_cts>, <&qupv3_se3_rts>,
|
||||
<&qupv3_se3_tx>, <&qupv3_se3_default_rx>;
|
||||
pinctrl-3 = <&qupv3_se3_default_cts>, <&qupv3_se3_default_rts>,
|
||||
<&qupv3_se3_default_tx>, <&qupv3_se3_default_rx>;
|
||||
qcom,wakeup-byte = <0xFD>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_i2c: i2c@4a94000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a94000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_i2c_sda_active>, <&qupv3_se5_i2c_scl_active>;
|
||||
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 5 3 64 0>,
|
||||
<&gpi_dma0 1 5 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_spi: spi@4a94000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a94000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
|
||||
interconnect-names = "qup-core", "qup-config", "qup-memory";
|
||||
interconnects =
|
||||
<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_spi_mosi_active>, <&qupv3_se5_spi_miso_active>,
|
||||
<&qupv3_se5_spi_clk_active>, <&qupv3_se5_spi_cs_active>;
|
||||
pinctrl-1 = <&qupv3_se5_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 5 1 64 0>,
|
||||
<&gpi_dma0 1 5 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Reference in New Issue
Block a user