mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
Merge "ARM: dts: msm: Add QUPv3 UART console and HSUART node for monaco"
This commit is contained in:
qctecmdr
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Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
commit
252f4fe1e2
@@ -10,19 +10,32 @@
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wakeup-parent = <&wakegic>;
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qupv3_se6_2uart_pins: qupv3_se6_2uart_pins {
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qupv3_se6_2uart_active: qupv3_se6_2uart_active {
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qupv3_se6_2uart_tx_active: qupv3_se6_2uart_tx_active {
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mux {
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pins = "gpio30", "gpio31";
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function = "qup06";
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pins = "gpio30";
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function = "qup0_l2";
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};
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config {
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pins = "gpio30", "gpio31";
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pins = "gpio30";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se3_2uart_rx_active: qupv3_se3_2uart_rx_active {
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mux {
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pins = "gpio31";
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function = "qup0_l3";
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};
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config {
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pins = "gpio31";
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drive-strength= <2>;
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bias-disable;
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};
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};
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qupv3_se6_2uart_sleep: qupv3_se6_2uart_sleep {
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mux {
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pins = "gpio30", "gpio31";
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@@ -768,15 +781,27 @@
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};
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qupv3_se5_4uart_pins: qupv3_se5_4uart_pins {
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qupv3_se5_default_ctsrtsrx:
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qupv3_se5_default_ctsrtsrx {
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qupv3_se5_default_cts: qupv3_se5_default_cts {
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mux {
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pins = "gpio26", "gpio27", "gpio29";
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pins = "gpio26";
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function = "gpio";
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};
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config {
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pins = "gpio26", "gpio27", "gpio29";
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pins = "gpio26";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se5_default_rts: qupv3_se5_default_rts {
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mux {
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pins = "gpio27";
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function = "gpio";
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};
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config {
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pins = "gpio27";
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drive-strength = <2>;
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bias-pull-down;
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};
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@@ -795,14 +820,27 @@
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};
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};
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qupv3_se5_ctsrx: qupv3_se5_ctsrx {
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qupv3_se5_default_rx: qupv3_se5_default_rx {
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mux {
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pins = "gpio26", "gpio29";
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function = "qup05";
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pins = "gpio29";
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function = "gpio";
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};
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config {
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pins = "gpio26", "gpio29";
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pins = "gpio29";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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qupv3_se5_cts: qupv3_se5_cts {
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mux {
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pins = "gpio26";
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function = "qup0_l0";
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};
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config {
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pins = "gpio26";
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drive-strength = <2>;
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bias-disable;
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};
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@@ -811,7 +849,7 @@
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qupv3_se5_rts: qupv3_se5_rts {
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mux {
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pins = "gpio27";
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function = "qup05";
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function = "qup0_l1";
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};
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config {
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@@ -824,7 +862,7 @@
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qupv3_se5_tx: qupv3_se5_tx {
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mux {
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pins = "gpio28";
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function = "qup05";
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function = "qup0_l2";
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};
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config {
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@@ -833,6 +871,19 @@
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bias-pull-up;
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};
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};
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qupv3_se5_rx: qupv3_se5_rx {
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mux {
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pins = "gpio29";
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function = "qup0_l3";
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};
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config {
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pins = "gpio29";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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/* WSA speaker reset pin1 */
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65
qcom/monaco-qupv3.dtsi
Normal file
65
qcom/monaco-qupv3.dtsi
Normal file
@@ -0,0 +1,65 @@
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&soc {
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/* QUPv3_0 wrapper instance */
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qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
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compatible = "qcom,geni-se-qup";
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reg = <0x4ac0000 0x2000>;
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#address-cells = <1>;
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#size-cells = <1>;
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clock-names = "m-ahb", "s-ahb";
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clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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iommus = <&apps_smmu 0xe3 0x0>;
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qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
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qcom,iommu-geometry = <0x40000000 0x10000000>;
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qcom,iommu-dma = "fastmap";
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dma-coherent;
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ranges;
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status = "ok";
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/* Debug UART Instance */
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qupv3_se6_2uart: qcom,qup_uart@4a98000 {
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compatible = "qcom,geni-debug-uart";
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reg = <0x4a98000 0x4000>;
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reg-names = "se_phys";
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interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qupv3_se6_2uart_tx_active>, <&qupv3_se3_2uart_rx_active>;
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pinctrl-1 = <&qupv3_se6_2uart_sleep>;
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status = "disabled";
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};
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/* HS UART Instance */
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qupv3_se5_4uart: qcom,qup_uart@4a94000 {
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compatible = "qcom,msm-geni-serial-hs";
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reg = <0x4a94000 0x4000>;
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reg-names = "se_phys";
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interrupts-extended = <&intc GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
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<&tlmm 29 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se-clk";
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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interconnects =
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<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
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<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
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<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
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pinctrl-names = "default", "active", "sleep", "shutdown";
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pinctrl-0 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
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<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
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pinctrl-1 = <&qupv3_se5_cts>, <&qupv3_se5_rts>,
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<&qupv3_se5_tx>, <&qupv3_se5_rx>;
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pinctrl-2 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
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<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
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pinctrl-3 = <&qupv3_se5_default_cts>, <&qupv3_se5_default_rts>,
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<&qupv3_se5_default_tx>, <&qupv3_se5_default_rx>;
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qcom,wakeup-byte = <0xFD>;
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status = "disabled";
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};
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};
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};
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@@ -21,6 +21,8 @@
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aliases {
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sdhc0 = &sdhc_1; /*SDC1 eMMC slot*/
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serial0 = &qupv3_se6_2uart;
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hsuart0 = &qupv3_se5_4uart;
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};
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firmware: firmware {};
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@@ -1214,6 +1216,7 @@
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#include "monaco-regulators.dtsi"
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#include "monaco-pmic.dtsi"
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#include "monaco-pinctrl.dtsi"
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#include "monaco-qupv3.dtsi"
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#include "monaco-coresight.dtsi"
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#include "msm-arm-smmu-monaco.dtsi"
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#include "monaco-dma-heaps.dtsi"
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@@ -1274,3 +1277,7 @@
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io-channels= <&pm5100_charger PSY_IIO_USB_REAL_TYPE>;
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io-channel-names = "chg_type";
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};
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&qupv3_se6_2uart {
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status = "ok";
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};
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