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dt-bindings: Add bindings for LLCC-perfmon

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Add bindings to move LLCC-perfmon to its own node.

Change-Id: I19ad3fa6502b04dad072fb13464ceea992fbd0c6
This commit is contained in:
Elliot Berman
2021-08-12 21:35:42 -07:00
committed by Gerrit - the friendly Code Review server
parent 9d040f7970
commit 25bb2adbcb
1 changed files with 23 additions and 6 deletions
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29
bindings/arm/msm/qcom,llcc.txt
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@@ -35,6 +35,22 @@ Properties:
Definition: The interrupt is associated with the llcc edac device.
It's used for llcc cache single and double bit error detection
and reporting.
Example:
cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
LLCC Performance Monitor
===
- compatible:
Usage: required
Value type: <string>
Definition: must be "qcom,llcc-perfom"
- clocks:
Usage: required
@@ -51,10 +67,11 @@ Properties:
Example:
cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_aop QDSS_CLK>;
clock-names = "qdss_clk";
...
llcc-perfmon {
compatible = "qcom,llcc-perfmon";
clocks = <&aoss_qmp QDSS_CLK>;
clock-names = "qdss_clk";
};
...
};