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https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Add boot stats node for Kalama"
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36
bindings/arm/msm/mpm_counter.yaml
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36
bindings/arm/msm/mpm_counter.yaml
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@@ -0,0 +1,36 @@
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%YAML 1.2
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---
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MSM MPM sleep counter (mpm-v2)
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maintainers:
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- Prakruthi Deepak Heragu <pheragu@quicinc.com>
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description: |
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The MPM provides a timetick that starts when the device is powered up and
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is not reset by any of the boot loaders or the HLOS. The MPM timetick counter
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driver provides an api to get this value.
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properties:
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compatible:
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const: qcom,mpm2-sleep-counter
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reg:
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description: Specifies the physical address of the timetick count register.
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clock-frequency:
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description: the physical counter frequency.
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required:
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- compatible
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- reg
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example:
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- |
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qcom,mpm2-sleep-counter@4a3000 {
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compatible = "qcom,mpm2-sleep-counter";
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reg = <0x4a3000 0x1000>;
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clock-frequency = <32768>;
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};
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@@ -628,6 +628,54 @@
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interrupt-controller;
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};
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qcom,msm-imem@146aa000 {
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compatible = "qcom,msm-imem";
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reg = <0x146aa000 0x1000>;
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ranges = <0x0 0x146aa000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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mem_dump_table@10 {
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compatible = "qcom,msm-imem-mem_dump_table";
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reg = <0x10 0x8>;
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};
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restart_reason@65c {
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compatible = "qcom,msm-imem-restart_reason";
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reg = <0x65c 0x4>;
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};
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dload_type@1c {
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compatible = "qcom,msm-imem-dload-type";
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reg = <0x1c 0x4>;
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};
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boot_stats@6b0 {
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compatible = "qcom,msm-imem-boot_stats";
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reg = <0x6b0 0x20>;
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};
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kaslr_offset@6d0 {
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compatible = "qcom,msm-imem-kaslr_offset";
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reg = <0x6d0 0xc>;
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};
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pil@94c {
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compatible = "qcom,pil-reloc-info";
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reg = <0x94c 0xc8>;
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};
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pil@6dc {
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compatible = "qcom,msm-imem-pil-disable-timeout";
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reg = <0x6dc 0x4>;
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};
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diag_dload@c8 {
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compatible = "qcom,msm-imem-diag-dload";
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reg = <0xc8 0xc8>;
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};
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};
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tlmm: pinctrl@f000000 {
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compatible = "qcom,kalama-pinctrl";
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reg = <0x0F000000 0x1000000>;
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@@ -1236,6 +1284,12 @@
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compatible = "syscon";
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reg = <0x1fc0000 0x30000>;
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};
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qcom,mpm2-sleep-counter@c221000 {
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compatible = "qcom,mpm2-sleep-counter";
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reg = <0xc221000 0x1000>;
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clock-frequency = <32768>;
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};
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};
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&firmware {
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