Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Add PDC interrupt controller for SM8150"

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qctecmdr
2022-01-27 09:56:24 -08:00
committed by Gerrit - the friendly Code Review server
parent 9f7496f28c aab077dac8
commit 3c792847c0
3 changed files with 51 additions and 12 deletions
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1
bindings/interrupt-controller/qcom,pdc.txt
View File

@@ -21,6 +21,7 @@ Properties:
- "qcom,sc7180-pdc": For SC7180
- "qcom,sc7280-pdc": For SC7280
- "qcom,sdm845-pdc": For SDM845
- "qcom,sdm8150-pdc": For SM8150
- "qcom,sdm8250-pdc": For SM8250
- "qcom,sdm8350-pdc": For SM8350

1
qcom/sm8150-pinctrl.dtsi
View File

@@ -12,6 +12,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
wakeup-parent = <&pdc>;
ufs_dev_reset_assert: ufs_dev_reset_assert {
config {

61
qcom/sm8150.dtsi
View File

@@ -434,6 +434,15 @@
interrupt-parent = <&intc>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8150-pdc", "qcom,pdc";
reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
@@ -514,22 +523,50 @@
<0x18210000 0x10000>,
<0x18220000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
qcom,drv-count = <3>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 1>,
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
rpmhcc: clock-controller {
compatible = "qcom,sm8150-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
status = "okay";
apps_rsc_drv2: drv@2 {
qcom,drv-id = <2>;
qcom,tcs-offset = <0xd00>;
channel@0 {
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>,
<FAST_PATH_TCS 0>;
};
rpmhcc: clock-controller {
compatible = "qcom,sm8150-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
status = "okay";
};
};
};
disp_rsc: rsc@af20000 {
label = "disp_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0xaf20000 0x10000>;
reg-names = "drv-0";
qcom,drv-count = <1>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
disp_rsc_drv0: drv@0 {
qcom,drv-id = <0>;
qcom,tcs-offset = <0x1c00>;
channel@0 {
qcom,tcs-config = <SLEEP_TCS 1>,
<WAKE_TCS 1>,
<ACTIVE_TCS 2>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 0>;
};
};
};