Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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ARM: dts: msm: Add the PCIE/USB fixed clocks for Cinder

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Update the fixed clock phandles for GCC clock node.

Change-Id: I791600e7b9fe30ac154c6d44f741fc1ca1c54935
This commit is contained in:
Taniya Das
2022-05-20 23:50:50 +05:30
parent 78737ffa01
commit 40980df01e
2 changed files with 33 additions and 4 deletions
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6
qcom/cinder-rumi.dtsi
View File

@@ -100,8 +100,10 @@
};
&gcc {
clocks = <&bi_tcxo>, <&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
clocks = <&bi_tcxo>, <&sleep_clk>, <&pcie_0_pipe_clk>,
<&pcie_0_phy_aux_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo", "sleep_clk", "pcie_0_pipe_clk",
"pcie_0_phy_aux_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk";
};
&tsens0 {

31
qcom/cinder.dtsi
View File

@@ -921,13 +921,40 @@
#reset-cells = <1>;
};
pcie_0_pipe_clk: pcie_0_pipe_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_0_pipe_clk";
#clock-cells = <0>;
};
pcie_0_phy_aux_clk: pcie_0_phy_aux_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_0_phy_aux_clk";
#clock-cells = <0>;
};
usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <0>;
};
gcc: clock-controller@80000 {
compatible = "qcom,cinder-gcc", "syscon";
reg = <0x80000 0x1f4200>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
clock-names = "bi_tcxo", "sleep_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
<&pcie_0_pipe_clk>,
<&pcie_0_phy_aux_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo", "sleep_clk",
"pcie_0_pipe_clk",
"pcie_0_phy_aux_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
protected-clocks = <GCC_AGGRE_NOC_ECPRI_DMA_CLK>,
<GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC>,
<GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC>,