Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Enable support for sdcc1 on sa410"

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qctecmdr
2022-10-17 00:34:49 -07:00
committed by Gerrit - the friendly Code Review server
parent 2b43cdfd67 3679382c9f
commit 44ae0be5b7
6 changed files with 145 additions and 0 deletions
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16
qcom/sa410m-idp.dtsi
View File

@@ -3,3 +3,19 @@
&qnand_1 {
status = "ok";
};
&sdhc_1 {
status = "ok";
vdd-supply = <&L20A>;
qcom,vdd-voltage-level = <2856000 2856000>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L14A>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 325000>;
max-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};

4
qcom/sa410m-nand-ccard.dts
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@@ -12,3 +12,7 @@
&qnand_1 {
status = "ok";
};
&sdhc_1 {
status = "disabled";
};

4
qcom/sa410m-nand-idp.dts
View File

@@ -12,3 +12,7 @@
&qnand_1 {
status = "ok";
};
&sdhc_1 {
status = "disabled";
};

50
qcom/sa410m-pinctrl.dtsi
View File

@@ -691,4 +691,54 @@
};
};
};
sdc1_on: sdc1_on {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_off: sdc1_off {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};
};

23
qcom/sa410m-rumi.dtsi
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@@ -42,3 +42,26 @@
status = "ok";
};
&sdhc_1 {
status = "ok";
vdd-supply = <&L20A>;
qcom,vdd-voltage-level = <2856000 2856000>;
qcom,vdd-current-level = <0 570000>;
vdd-io-supply = <&L14A>;
qcom,vdd-io-always-on;
qcom,vdd-io-lpm-sup;
qcom,vdd-io-voltage-level = <1800000 1800000>;
qcom,vdd-io-current-level = <0 325000>;
/delete-property/ mmc-ddr-1_8v;
/delete-property/ mmc-hs200-1_8v;
/delete-property/ mmc-hs400-1_8v;
/delete-property/ mmc-hs400-enhanced-strobe;
max-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
};

48
qcom/sa410m.dtsi
View File

@@ -25,6 +25,7 @@
aliases {
serial0 = &qupv3_se4_2uart;
qpic_nand1 = &qnand_1;
mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
};
firmware: firmware {};
@@ -521,6 +522,53 @@
qcom,iommu-dma = "bypass";
status = "disabled";
};
sdhc_1: sdhci@4744000 {
status = "disabled";
compatible = "qcom,sdhci-msm-v5";
reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
reg-names = "hc", "cqhci";
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
bus-width = <8>;
non-removable;
supports-cqe;
no-sd;
no-sdio;
qcom,restore-after-cx-collapse;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
cap-mmc-hw-reset;
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
<&gcc GCC_SDCC1_AHB_CLK>;
clock-names = "core", "iface";
/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>;
/* Add dt entry for gcc hw reset */
//resets = <&gcc GCC_EMMC_BCR>;
//reset-names = "core_reset";
iommus = <&apps_smmu 0xC0 0x0>;
qcom,iommu-dma = "bypass";
qos0 {
mask = <0x0f>;
vote = <44>;
};
};
};
#include "sa410m-stub-regulators.dtsi"