Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Add LPM modes, mpm, rpm_smd and stats nodes for SA410m_auto"

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qctecmdr
2022-10-18 18:32:50 -07:00
committed by Gerrit - the friendly Code Review server
parent 0786b42591 9ac7aa2795
commit 47c73c6ffa
2 changed files with 96 additions and 1 deletions
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1
bindings/interrupt-controller/qcom,mpm.txt
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@@ -27,6 +27,7 @@ Properties:
"qcom,mpm-khaje"
"qcom,mpm-monaco"
"qcom,mpm-scuba"
"qcom,mpm-sa410m"
- interrupts:
Usage: required

96
qcom/sa410m.dtsi
View File

@@ -41,6 +41,8 @@
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
cpu-idle-states = <&SILVER_OFF>;
power-domains = <&CPU_PD0>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
@@ -65,6 +67,8 @@
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
cpu-idle-states = <&SILVER_OFF>;
power-domains = <&CPU_PD1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
@@ -86,6 +90,8 @@
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF>;
power-domains = <&CPU_PD2>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
@@ -106,6 +112,8 @@
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
cpu-idle-states = <&SILVER_OFF>;
power-domains = <&CPU_PD3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
@@ -142,9 +150,56 @@
};
};
idle-states {
SILVER_OFF: silver-c3 { /* C3 */
compatible = "arm,idle-state";
idle-state-name = "pc";
entry-latency-us = <297>;
exit-latency-us = <324>;
min-residency-us = <1110>;
arm,psci-suspend-param = <0x40000003>;
local-timer-stop;
};
SILVER_CLUSTER_D3: silver-cluster-d3 { /* D3 */
compatible = "domain-idle-state";
idle-state-name = "pwr-l2-pc";
entry-latency-us = <800>;
exit-latency-us = <2118>;
min-residency-us = <7376>;
arm,psci-suspend-param = <0x41000043>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: cpu-pd0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD1: cpu-pd1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD2: cpu-pd2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CPU_PD3: cpu-pd3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
};
CLUSTER_PD0: cluster-pd0 {
#power-domain-cells = <0>;
domain-idle-states = <&SILVER_CLUSTER_D3>;
};
};
chosen {
@@ -296,6 +351,45 @@
#gpio-cells = <0>;
};
mpm: interrupt-controller@45f01b8 {
compatible = "qcom,mpm-sa410m", "qcom,mpm";
reg = <0x45f01b8 0x1000>,
<0xf111008 0x4>, /* MSM_APCS_GCC_BASE 4K */
<0xf121000 0x1000>;
reg-names = "vmpm", "ipc", "timer";
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
qcom,num-mpm-irqs = <96>;
interrupt-controller;
interrupt-parent = <&intc>;
#interrupt-cells = <2>;
};
rpm_bus: qcom,rpm-smd {
compatible = "qcom,rpm-smd";
rpm-channel-name = "rpm_requests";
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
power-domains = <&CLUSTER_PD>;
rpm-channel-type = <15>; /* SMD_APPS_RPM */
};
cluster-device {
compatible = "qcom,lpm-cluster-dev";
power-domains = <&CLUSTER_PD>;
};
rpm-sleep-stats@4690000 {
compatible = "qcom,rpm-sleep-stats";
reg = <0x04690000 0x400>;
};
qcom,rpm-master-stats@45f0150 {
compatible = "qcom,rpm-master-stats";
reg = <0x45f0150 0x5000>;
qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ";
qcom,master-stats-version = <2>;
qcom,master-offset = <4096>;
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
@@ -383,7 +477,7 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
//wakeup-parent = <&wakegic>;
wakeup-parent = <&mpm>;
};
qcom-secure-buffer {