Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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ARM: dts: msm: change PIN func of qup2_se0 per pinctrl driver

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This change is to modify the pinctrl function for GPIO no -
56, 57, 58, 59 for QUP2 SE0 as per the IPCAT. This also needs
a change from pinctrl.c to define the same name in the driver.

Change-Id: I1eafb7565c6f4eedcae6dcc6f48b233ddfbf0092
This commit is contained in:
Mukesh Kumar Savaliya
2022-05-20 10:15:14 +05:30
committed by Gerrit - the friendly Code Review server
parent 2faffd49f9
commit 48dc18df7c
1 changed files with 6 additions and 6 deletions
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12
qcom/kalama-pinctrl.dtsi
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@@ -1078,7 +1078,7 @@
qupv3_se8_i2c_sda_active: qupv3_se8_i2c_sda_active {
mux {
pins = "gpio56";
function = "qup2_se0_l0";
function = "qup2_se0_l0_mira";
};
config {
@@ -1091,7 +1091,7 @@
qupv3_se8_i2c_scl_active: qupv3_se8_i2c_scl_active {
mux {
pins = "gpio57";
function = "qup2_se0_l1";
function = "qup2_se0_l1_mira";
};
config {
@@ -1187,7 +1187,7 @@
qupv3_se8_spi_miso_active: qupv3_se8_spi_miso_active {
mux {
pins = "gpio56";
function = "qup2_se0_l0";
function = "qup2_se0_l0_mira";
};
config {
@@ -1200,7 +1200,7 @@
qupv3_se8_spi_mosi_active: qupv3_se8_spi_mosi_active {
mux {
pins = "gpio57";
function = "qup2_se0_l1";
function = "qup2_se0_l1_mira";
};
config {
@@ -1213,7 +1213,7 @@
qupv3_se8_spi_clk_active: qupv3_se8_spi_clk_active {
mux {
pins = "gpio58";
function = "qup2_se0_l2";
function = "qup2_se0_l2_mira";
};
config {
@@ -1226,7 +1226,7 @@
qupv3_se8_spi_cs_active: qupv3_se8_spi_cs_active {
mux {
pins = "gpio59";
function = "qup2_se0_l3";
function = "qup2_se0_l3_mira";
};
config {