mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
Merge "ARM: dts: msm: Add EP PCIe and MHI related DT entries on sdxpinn"
This commit is contained in:
qctecmdr
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Gerrit - the friendly Code Review server
Gerrit - the friendly Code Review server
commit
5a769b63ba
@@ -201,4 +201,46 @@
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};
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};
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};
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pcie_ep {
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pcie_ep_clkreq_default: pcie_ep_clkreq_default {
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mux {
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pins = "gpio43";
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function = "pcie0_clkreq_n";
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};
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config {
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pins = "gpio43";
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drive-strength = <2>;
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bias-disable;
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input-enable;
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};
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};
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pcie_ep_perst_default: pcie_ep_perst_default {
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mux {
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pins = "gpio44";
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function = "gpio";
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};
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config {
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pins = "gpio44";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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pcie_ep_wake_default: pcie_ep_wake_default {
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mux {
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pins = "gpio42";
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function = "gpio";
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};
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config {
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pins = "gpio42";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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};
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@@ -113,3 +113,25 @@
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dr_mode = "peripheral";
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};
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};
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&pcie_ep {
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reg = <0x48003800 0x10000>,
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<0x48000000 0xf20>,
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<0x48000f20 0xa8>,
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<0x48001000 0x2000>,
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<0x01bf0000 0x4000>,
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<0x01bf7000 0x2000>,
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<0x01bf4000 0x1000>,
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<0x01bf7500 0x4>;
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reg-names = "msi", "dm_core", "elbi", "iatu",
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"parf", "phy", "mmio", "rumi";
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qcom,pcie-link-speed = <1>;
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qcom,tcsr-not-supported;
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status = "ok";
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};
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&mhi_device {
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status = "ok";
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};
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@@ -3,6 +3,8 @@
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/soc/qcom,ipcc.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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/ {
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model = "Qualcomm Technologies, Inc. SDXPINN";
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@@ -649,6 +651,109 @@
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thermal_zones: thermal-zones {
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};
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pcie_ep: qcom,pcie@0x48000000 {
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compatible = "qcom,pcie-ep";
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reg = <0x48003800 0x1000>,
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<0x48000000 0xf20>,
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<0x48000f20 0xa8>,
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<0x48001000 0x2000>,
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<0x01bf0000 0x4000>,
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<0x01bf7000 0x2000>,
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<0x01bf4000 0x1000>,
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<0x01fcb000 0x1000>,
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<0x0c2fa000 0x4>;
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reg-names = "msi", "dm_core", "elbi", "iatu",
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"parf", "phy", "mmio", "tcsr_pcie_perst_en",
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"aoss_cc_reset";
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#address-cells = <0>;
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interrupt-parent = <&pcie_ep>;
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interrupts = <0>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xffffffff>;
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interrupt-map = <0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int_global";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_ep_clkreq_default
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&pcie_ep_perst_default
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&pcie_ep_wake_default>;
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clkreq-gpio = <&tlmm 43 GPIO_ACTIVE_HIGH>;
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perst-gpio = <&tlmm 44 GPIO_ACTIVE_HIGH>;
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wake-gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
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gdsc-vdd-supply = <&gcc_pcie_gdsc>;
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gdsc-phy-vdd-supply = <&gcc_pcie_phy_gdsc>;
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vreg-1p8-supply = <&L1B>;
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vreg-0p9-supply = <&L4B>;
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vreg-mx-supply = <&VDD_MXA_LEVEL>;
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qcom,vreg-1p8-voltage-level = <1200000 1200000 30000>;
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qcom,vreg-0p9-voltage-level = <912000 880000 177000>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM
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0>;
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clocks = <&gcc GCC_PCIE_PIPE_CLK>,
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<&gcc GCC_PCIE_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_AUX_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_SLEEP_CLK>,
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<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_PIPE_CLK_SRC>,
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<&pcie_pipe_clk>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk",
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"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
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"pcie_aux_clk", "pcie_ldo",
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"pcie_sleep_clk",
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"pcie_slv_q2a_axi_clk",
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"pcie_pipe_clk_mux",
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"pcie_pipe_clk_ext_src",
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"pcie_0_ref_clk_src";
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resets = <&gcc GCC_PCIE_BCR>,
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<&gcc GCC_PCIE_PHY_BCR>;
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reset-names = "pcie_core_reset",
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"pcie_phy_reset";
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qcom,pcie-vendor-id = /bits/ 16 <0x17cb>;
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qcom,pcie-device-id = /bits/ 16 <0x0309>;
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qcom,pcie-link-speed = <4>;
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qcom,pcie-phy-ver = <7>;
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qcom,pcie-active-config;
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qcom,pcie-aggregated-irq;
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qcom,pcie-mhi-a7-irq;
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qcom,phy-status-reg2 = <0x1214>;
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qcom,mhi-soc-reset-offset = <0xb01b8>;
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qcom,aoss-rst-clr;
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qcom,aux-clk = <0x13>;
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status = "disabled";
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};
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mhi_device: mhi_dev@1bf4000 {
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compatible = "qcom,msm-mhi-dev";
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reg = <0x1bf4000 0x1000>;
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reg-names = "mhi_mmio_base";
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qcom,mhi-ep-msi = <0>;
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qcom,mhi-version = <0x1000000>;
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qcom,use-mhi-dma-software-channel;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mhi-device-inta";
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qcom,mhi-ifc-id = <0x030917cb>;
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qcom,mhi-interrupt;
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qcom,no-m0-timeout;
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status = "disabled";
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};
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mhi_net_device: qcom,mhi_net_dev {
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compatible = "qcom,msm-mhi-dev-net";
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status = "disabled";
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};
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qcom,sps {
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compatible = "qcom,msm-sps-4k";
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qcom,pipe-attr-ee;
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