Merge "ARM: dts: msm: Enable nand support for sa410m"

This commit is contained in:
qctecmdr
2022-10-14 03:09:25 -07:00
committed by Gerrit - the friendly Code Review server
7 changed files with 53 additions and 0 deletions

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@@ -8,3 +8,7 @@
qcom,msm-id=<560 0x10000>;
qcom,board-id = <25 0x0>;
};
&qnand_1 {
status = "disabled";
};

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@@ -8,3 +8,7 @@
qcom,msm-id=<560 0x10000>;
qcom,board-id = <34 0x0>;
};
&qnand_1 {
status = "disabled";
};

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@@ -1 +1,5 @@
#include "sa410m.dtsi"
&qnand_1 {
status = "ok";
};

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@@ -8,3 +8,7 @@
qcom,msm-id=<560 0x10000>;
qcom,board-id = <25 0x1>;
};
&qnand_1 {
status = "ok";
};

View File

@@ -8,3 +8,7 @@
qcom,msm-id=<560 0x10000>;
qcom,board-id = <34 0x1>;
};
&qnand_1 {
status = "ok";
};

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@@ -37,3 +37,8 @@
clocks = <&bi_tcxo>, <&bi_tcxo_ao>, <&pcie_0_pipe_clk>,
<&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
};
&qnand_1 {
status = "ok";
};

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@@ -24,6 +24,7 @@
aliases {
serial0 = &qupv3_se4_2uart;
qpic_nand1 = &qnand_1;
};
firmware: firmware {};
@@ -480,6 +481,33 @@
compatible = "qcom,msm-sps-4k";
qcom,pipe-attr-ee;
};
qnand_1: nand@0x4840000 {
compatible = "qcom,msm-nand";
reg = <0x4840000 0x1000>,
<0x4844000 0x1c000>;
reg-names = "nand_phys",
"bam_phys";
qcom,reg-adjustment-offset = <0x4000>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "bam_irq";
clock-names = "core_clk";
clocks = <&rpmcc RPM_SMD_QPIC_CLK>;
//interconnects = <&system_noc MASTER_QPIC &mc_virt SLAVE_EBI1>;
interconnect-names = "nand-ddr";
qcom,msm-bus,name = "qpic_nand";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<0 0>,
/* Voting for max b/w on PNOC bus for now */
<1057800 725760>;
iommus = <&apps_smmu 0x100 0x7>;
qcom,iommu-dma = "bypass";
status = "disabled";
};
};
#include "sa410m-stub-regulators.dtsi"