Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
2
0
Fork 0
mirror of https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees synced 2026-02-01 05:00:27 +00:00
Code Issues Packages Projects Releases Wiki Activity

ARM: dts: msm: Set QSERDES_COM_SYSCLK_EN to 0x8 for PCIe2 PHY for sdxpinn

Browse Source 
For PCIe 2 PHY setting of QSERDES_COM_SYSCLK_EN to 0x4 which is
internal diff cml clock, PHY is not coming up and hence changed the
PCIe 2 PHY setting of QSERDES_COM_SYSCLK_EN to 0x8 which is SE cmos clock.

Corrected SLV_Q2A_AXI_CLK clock for PCIe2.

Updated reset names of core and phy of PCIe0.

Change-Id: Ib227f03e2ddc4c581d538152e54fe036aef29895
This commit is contained in:
Jyothi Kumar Seerapu
2022-10-28 19:23:14 +05:30
committed by Gerrit - the friendly Code Review server
parent 2d3606f3aa
commit 680058afe8
1 changed files with 4 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
qcom/sdxpinn-pcie.dtsi
View File

@@ -105,8 +105,8 @@
<0>, <0>, <0>, <0>;
resets = <&gcc GCC_PCIE_BCR>,
<&gcc GCC_PCIE_PHY_BCR>;
reset-names = "pcie_core_reset",
"pcie_phy_reset";
reset-names = "pcie_0_core_reset",
"pcie_0_phy_reset";
qcom,smmu-sid-base = <0x0800>;
iommu-map = <0x0 &apps_smmu 0x0800 0x1>,
@@ -648,7 +648,7 @@
<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_2_SLV_AXI_CLK>,
<&gcc GCC_PCIE_2_CLKREF_EN>,
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_2_PIPE_DIV2_CLK>,
<&gcc GCC_PCIE_2_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_2_PIPE_CLK_SRC>,
@@ -718,7 +718,7 @@
0x00e0 0x90 0x0
0x00e4 0x82 0x0
0x00f4 0x07 0x0
0x0110 0x04 0x0
0x0110 0x08 0x0
0x0120 0x42 0x0
0x0140 0x14 0x0
0x0164 0x34 0x0