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680058afe8
For PCIe 2 PHY setting of QSERDES_COM_SYSCLK_EN to 0x4 which is internal diff cml clock, PHY is not coming up and hence changed the PCIe 2 PHY setting of QSERDES_COM_SYSCLK_EN to 0x8 which is SE cmos clock. Corrected SLV_Q2A_AXI_CLK clock for PCIe2. Updated reset names of core and phy of PCIe0. Change-Id: Ib227f03e2ddc4c581d538152e54fe036aef29895