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ARM: dts: msm: Add support for both primary and secondary ports on SA8155

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On SA8155 the primary USB port is HS capable and secondary USB
port is SS capable.
Add support for primary USB controller and HSPHY, secondary USB
controller and HSPHY, SSPHY for the same.

Change-Id: I62e9b10d6a938b72ecc66221a1b2dfa9d34c3fb5
This commit is contained in:
Shashikala Katthi
2022-02-15 16:38:31 +05:30
parent 734b63cbfd
commit 7116f4d7b5
2 changed files with 318 additions and 0 deletions
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317
qcom/sm8150-usb.dtsi Normal file
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@@ -0,0 +1,317 @@
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
#include <dt-bindings/phy/qcom,sm8150-qmp-usb3.h>
&soc {
/* Primary USB port related controller */
usb0: ssusb@a600000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0xa600000 0x100000>;
reg-names = "core_base";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 9 IRQ_TYPE_EDGE_RISING>,
<&pdc 8 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "pwr_event_irq","dp_hs_phy_irq",
"dm_hs_phy_irq";
qcom,use-pdc-interrupts;
USB3_GDSC-supply = <&usb30_prim_gdsc>;
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
/*
* GCC_USB3_SEC_CLKREF_CLK provides ref_clk for both
* USB instances. Hence GCC_USB3_PRIM_CLKREF_CLK is not
* used here.
*/
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk", "xo";
resets = <&gcc GCC_USB30_PRIM_BCR>;
reset-names = "core_reset";
qcom,core-clk-rate = <200000000>;
qcom,core-clk-rate-hs = <66666667>;
qcom,ignore-wakeup-src-in-hostmode;
interconnect-names = "usb-ddr", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0xa600000 0xcd00>;
iommus = <&apps_smmu 0x140 0x0>;
qcom,iommu-dma = "atomic";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,is-utmi-l1-suspend;
snps,usb2-gadget-lpm-disable;
tx-fifo-resize;
maximum-speed = "high-speed";
dr_mode = "otg";
usb-role-switch;
};
};
/* Primary USB port related High Speed PHY */
usb2_phy0: hsphy@88e2000 {
compatible = "qcom,usb-hsphy-snps-femto";
reg = <0x88e2000 0x110>,
<0x007801f8 0x4>;
reg-names = "hsusb_phy_base",
"phy_rcal_reg";
vdd-supply = <&L5A>;
vdda18-supply = <&L12A>;
vdda33-supply = <&L2A>;
qcom,vdd-voltage-level = <0 880000 880000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref_clk_src";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
reset-names = "phy_reset";
qcom,param-override-seq = <0x43 0x70>;
qcom,rcal-mask = <0x1e00000>;
};
usb_nop_phy: usb_nop_phy {
compatible = "usb-nop-xceiv";
};
/* Secondary USB port related controller */
usb1: ssusb@a800000 {
compatible = "qcom,dwc-usb3-msm";
reg = <0x0a800000 0x100000>;
reg-names = "core_base";
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 11 IRQ_TYPE_EDGE_RISING>,
<&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "pwr_event_irq","dp_hs_phy_irq",
"ss_phy_irq","dm_hs_phy_irq";
qcom,use-pdc-interrupts;
qcom,default-mode-host;
qcom,ignore-wakeup-src-in-hostmode;
USB3_GDSC-supply = <&usb30_sec_gdsc>;
clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
"utmi_clk", "sleep_clk", "xo";
resets = <&gcc GCC_USB30_SEC_BCR>;
reset-names = "core_reset";
qcom,core-clk-rate = <200000000>;
qcom,core-clk-rate-hs = <66666667>;
interconnect-names = "usb-ddr", "ddr-usb";
interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;
dwc3@a800000 {
compatible = "snps,dwc3";
reg = <0x0a800000 0xd941>;
iommus = <&apps_smmu 0x160 0x0>;
qcom,iommu-dma = "atomic";
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb2_phy1>, <&usb_qmp_phy>;
snps,disable-clk-gating;
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,ssp-u3-u0-quirk;
snps,is-utmi-l1-suspend;
snps,usb2-gadget-lpm-disable;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,force-gen1;
tx-fifo-resize;
maximum-speed = "super-speed";
dr_mode = "otg";
usb-role-switch;
};
};
/* Secondary USB port related High Speed PHY */
usb2_phy1: hsphy@88e3000 {
compatible = "qcom,usb-hsphy-snps-femto";
reg = <0x88e3000 0x110>,
<0x007801f8 0x4>;
reg-names = "hsusb_phy_base",
"phy_rcal_reg";
vdd-supply = <&L5A>;
vdda18-supply = <&L12A>;
vdda33-supply = <&L2A>;
qcom,vdd-voltage-level = <0 880000 880000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref_clk_src";
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
reset-names = "phy_reset";
qcom,param-override-seq = <0x43 0x70
0x01 0xb0>;
qcom,rcal-mask = <0x1e00000>;
pinctrl-names = "default";
pinctrl-0 = <&usb2phy_ac_en2_default>;
};
/* Secondary USB port related QMP PHY */
usb_qmp_phy: ssphy@88eb000 {
compatible = "qcom,usb-ssphy-qmp-v2";
reg = <0x88eb000 0x1000>,
<0x088eb88c 0x4>;
reg-names = "qmp_phy_base",
"pcs_clamp_enable_reg";
vdd-supply = <&L5A>;
qcom,vdd-voltage-level = <0 880000 880000>;
qcom,vdd-max-load-uA = <47000>;
core-supply = <&L8C>;
qcom,qmp-phy-init-seq =
/* <reg_offset, value, delay> */
<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0
USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0
USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x02 0
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0
USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0
USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0
USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0
USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0
USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xa4 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37 0
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f 0
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xaf 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb6 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0
USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0
USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0
USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0
USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a 0
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x00 0
USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0
USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04 0
USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0
USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0
USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20 0
USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0
USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0
USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95 0
USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0xe4 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0xd0 0
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0
USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0
USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0
USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0
USB3_UNI_PCS_CDR_RESET_TIME 0x0a 0
USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0
USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0
USB3_UNI_PCS_EQ_CONFIG1 0x4b 0
USB3_UNI_PCS_EQ_CONFIG5 0x10 0
USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0
USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0
0xffffffff 0xffffffff 0x00>;
qcom,qmp-phy-reg-offset =
<USB3_UNI_PCS_PCS_STATUS1
USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
USB3_UNI_PCS_POWER_DOWN_CONTROL
USB3_UNI_PCS_SW_RESET
USB3_UNI_PCS_START_CONTROL>;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
"ref_clk", "com_aux_clk";
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
reset-names = "phy_reset", "phy_phy_reset";
};
};

1
qcom/sm8150.dtsi
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@@ -1528,6 +1528,7 @@
#include "sm8150-gdsc.dtsi"
#include "msm-arm-smmu-sm8150.dtsi"
#include "sm8150-smp2p.dtsi"
#include "sm8150-usb.dtsi"
&emac_gdsc {
status = "ok";