mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:04:24 +00:00
Merge b1bf903b97 on remote branch
Change-Id: I2c55b86b22bd84e6c0bcdb624817f4f582328d07
This commit is contained in:
Linux Build Service Account
@@ -247,6 +247,7 @@ compatible = "qcom,kona-rumi"
|
||||
compatible = "qcom,kona-mtp"
|
||||
compatible = "qcom,kona-cdp"
|
||||
compatible = "qcom,kona-qrd"
|
||||
compatible = "qcom,kona-iot"
|
||||
compatible = "qcom,lahaina-rumi"
|
||||
compatible = "qcom,lahaina-atp"
|
||||
compatible = "qcom,lahaina-mtp"
|
||||
|
||||
@@ -27,6 +27,7 @@ Properties:
|
||||
- "qcom,sdxpinn-pdc": For SDXPINN
|
||||
- "qcom,lemans-pdc": For lemans
|
||||
- "qcom,sdxbaagha-pdc": For SDXBAAGHA
|
||||
- "qcom,kona-pdc": For Kona
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
|
||||
@@ -185,6 +185,10 @@ conditions.
|
||||
- qcom,num-smr-override:
|
||||
Optional integer. See qcom,num-context-banks-override.
|
||||
|
||||
- qcom,multi-match-handoff-smr:
|
||||
Optional property. Should be included if one handoff SMR matches
|
||||
multiple SMRs.
|
||||
|
||||
** Deprecated properties:
|
||||
|
||||
- mmu-masters (deprecated in favour of the generic "iommus" binding) :
|
||||
|
||||
197
bindings/pinctrl/qcom,kona-pinctrl.txt
Normal file
197
bindings/pinctrl/qcom,kona-pinctrl.txt
Normal file
@@ -0,0 +1,197 @@
|
||||
Qualcomm Technologies, Inc. KONA TLMM block
|
||||
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
KONA platform.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "qcom,kona-pinctrl"
|
||||
|
||||
- reg:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: the base address and size of the TLMM register space.
|
||||
|
||||
- interrupts:
|
||||
Usage: required
|
||||
Value type: <prop-encoded-array>
|
||||
Definition: should specify the TLMM summary IRQ.
|
||||
|
||||
- interrupt-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as an interrupt controller
|
||||
|
||||
- #interrupt-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
- gpio-controller:
|
||||
Usage: required
|
||||
Value type: <none>
|
||||
Definition: identifies this node as a gpio controller
|
||||
|
||||
- #gpio-cells:
|
||||
Usage: required
|
||||
Value type: <u32>
|
||||
Definition: must be 2. Specifying the pin number and flags, as defined
|
||||
in <dt-bindings/gpio/gpio.h>
|
||||
|
||||
- wakeup-parent:
|
||||
Usage: optional
|
||||
Value type: <phandle>
|
||||
Definition: A phandle to the wakeup interrupt controller for the SoC.
|
||||
|
||||
- qcom,gpios-reserved:
|
||||
Usage: optional
|
||||
Value type: <int array>
|
||||
Definition: A list of reserved gpios that should not be used by the kernel drivers.
|
||||
|
||||
Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
|
||||
a general description of GPIO and interrupt bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
The pin configuration nodes act as a container for an arbitrary number of
|
||||
subnodes. Each of these subnodes represents some desired configuration for a
|
||||
pin, a group, or a list of pins or groups. This configuration can include the
|
||||
mux function to select on those pin(s)/group(s), and various pin configuration
|
||||
parameters, such as pull-up, drive strength, etc.
|
||||
|
||||
|
||||
PIN CONFIGURATION NODES:
|
||||
|
||||
The name of each subnode is not important; all subnodes should be enumerated
|
||||
and processed purely based on their content.
|
||||
|
||||
Each subnode only affects those parameters that are explicitly listed. In
|
||||
other words, a subnode that lists a mux function but no pin configuration
|
||||
parameters implies no information about any pin configuration parameters.
|
||||
Similarly, a pin subnode that describes a pullup parameter implies no
|
||||
information about e.g. the mux function.
|
||||
|
||||
|
||||
The following generic properties as defined in pinctrl-bindings.txt are valid
|
||||
to specify in a pin configuration subnode:
|
||||
|
||||
- pins:
|
||||
Usage: required
|
||||
Value type: <string-array>
|
||||
Definition: List of gpio pins affected by the properties specified in
|
||||
this subnode.
|
||||
|
||||
Valid pins are:
|
||||
gpio0-gpio149
|
||||
Supports mux, bias and drive-strength
|
||||
|
||||
sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
|
||||
sdc2_data sdc1_rclk
|
||||
Supports bias and drive-strength
|
||||
|
||||
- function:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: Specify the alternative function to be configured for the
|
||||
specified pins. Functions are only valid for gpio pins.
|
||||
Valid values are:
|
||||
|
||||
blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
|
||||
bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
|
||||
qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
|
||||
dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
|
||||
blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
|
||||
mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
|
||||
atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
|
||||
cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
|
||||
pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
|
||||
qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
|
||||
qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
|
||||
atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
|
||||
atest_usb20, atest_char0, dac_calib10, qdss_stm10,
|
||||
qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
|
||||
blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
|
||||
qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
|
||||
qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
|
||||
dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
|
||||
qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
|
||||
dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
|
||||
dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
|
||||
dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
|
||||
dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
|
||||
sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
|
||||
qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
|
||||
uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
|
||||
blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
|
||||
qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
|
||||
blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
|
||||
cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
|
||||
blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
|
||||
qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
|
||||
isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
|
||||
qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
|
||||
sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
|
||||
gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
|
||||
qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
|
||||
tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
|
||||
qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
|
||||
sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
|
||||
sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
|
||||
ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
|
||||
blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
|
||||
pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
|
||||
qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
|
||||
qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
|
||||
gpio
|
||||
|
||||
- bias-disable:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as no pull.
|
||||
|
||||
- bias-pull-down:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull down.
|
||||
|
||||
- bias-pull-up:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins should be configured as pull up.
|
||||
|
||||
- output-high:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
high.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- output-low:
|
||||
Usage: optional
|
||||
Value type: <none>
|
||||
Definition: The specified pins are configured in output mode, driven
|
||||
low.
|
||||
Not valid for sdc pins.
|
||||
|
||||
- drive-strength:
|
||||
Usage: optional
|
||||
Value type: <u32>
|
||||
Definition: Selects the drive strength for the specified pins, in mA.
|
||||
Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
|
||||
|
||||
Example:
|
||||
|
||||
tlmm: pinctrl@03000000 {
|
||||
compatible = "qcom,kona-pinctrl";
|
||||
reg = <0x03000000 0xdc2000>;
|
||||
interrupts = <0 208 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
wakeup-parent = <&pdc>;
|
||||
};
|
||||
@@ -47,6 +47,11 @@ on the Qualcomm Technologies inc ADSP Hexagon core.
|
||||
"qcom,monaco-adsp-pas"
|
||||
"qcom,monaco-modem-pas"
|
||||
"qcom,sdxpinn-modem-pas"
|
||||
"qcom,lemans-adsp-pas"
|
||||
"qcom,lemans-cdsp-pas"
|
||||
"qcom,lemans-cdsp1-pas"
|
||||
"qcom,lemans-gpdsp0-pas"
|
||||
"qcom,lemans-gpdsp1-pas"
|
||||
|
||||
- interrupts-extended:
|
||||
Usage: required
|
||||
|
||||
31
bindings/soc/qcom/hgsl-tcsr.txt
Normal file
31
bindings/soc/qcom/hgsl-tcsr.txt
Normal file
@@ -0,0 +1,31 @@
|
||||
Top Control and Status Register(TCSR) for HGSL
|
||||
|
||||
TCSR hardware contains compute signal sub-block, which allows drivers in hypervisor
|
||||
Linux to communicate with GPU hardware directly. This HGSL TCSR driver is to enable
|
||||
the TCSR compute signal hardware. There are multiple instances of compute signal.
|
||||
Each instance is either a signal sender or signal receiver.
|
||||
|
||||
The HGSL TCSR driver is built on top of generic TCSR driver, refer to
|
||||
Documentation/devicetree/bindings/mfd/qcom,tcsr.txt for the generic TCSR driver.
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "qcom,hgsl-tcsr-sender" or "qcom,hgsl-tcsr-receiver"
|
||||
- syscon : Point to the generic TCSR compute signal node
|
||||
- syscon-glb : Point to the generice TCSR node for compute signal global control.
|
||||
This is only needed by signal sender.
|
||||
- interrupts : Specify IRQ information used by the compute signal.
|
||||
This is only needed by signal receiver.
|
||||
|
||||
Examples:
|
||||
hgsl_tcsr_sender0: hgsl_tcsr_sender0 {
|
||||
compatible = "qcom,hgsl-tcsr-sender";
|
||||
syscon = <&tcsr_compute_signal_sender0>;
|
||||
syscon-glb = <&tcsr_compute_signal_glb>;
|
||||
};
|
||||
|
||||
hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 {
|
||||
compatible = "qcom,hgsl-tcsr-receiver";
|
||||
syscon = <&tcsr_compute_signal_receiver0>;
|
||||
interrupts = <0 238 0>;
|
||||
};
|
||||
|
||||
32
bindings/soc/qcom/hgsl.txt
Normal file
32
bindings/soc/qcom/hgsl.txt
Normal file
@@ -0,0 +1,32 @@
|
||||
* HGSL
|
||||
|
||||
HGSL(Hypervisor Graphics system layer) is graphics driver under the hypervisor system.
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "qcom,hgsl"
|
||||
|
||||
- reg : physical base address and length of the register set(s).
|
||||
|
||||
- reg-names : names corresponding to each reg property value.
|
||||
reg_hwver: HW version registers
|
||||
reg_doorbell_idx: address of GMUAO_DOORBELL_IDX
|
||||
|
||||
Optional properties:
|
||||
- db-off: Disable Doorbell feature but keep hgsl for ifence service
|
||||
- qcom,glb-db-senders : Point to possible nodes of HGSL TCSR sender. The user will select
|
||||
which sender to use. The driver will use TCSR compute signal to
|
||||
send signal to GPU.
|
||||
- qcom,glb-db-receivers : Point to possible nodes of HGSL TCSR receiver. The user will
|
||||
select which receiver to use. The driver will use TCSR compute
|
||||
signal to receive signal from GPU.
|
||||
|
||||
Example:
|
||||
msm_gpu_hyp {
|
||||
compatible = "qcom,hgsl";
|
||||
reg = <0x2c00000 0x8>, <0x2c8f000 0x4>;
|
||||
reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx";
|
||||
|
||||
db-off = <0>;
|
||||
qcom,glb-db-senders = <&hgsl_tcsr_sender0 &hgsl_tcsr_sender1>;
|
||||
qcom,glb-db-receivers = <&hgsl_tcsr_receiver0 &hgsl_tcsr_receiver1>;
|
||||
};
|
||||
@@ -122,6 +122,16 @@ bengal-dtb-$(CONFIG_ARCH_KHAJE) += \
|
||||
bengal-overlays-dtb-$(CONFIG_ARCH_KHAJE) += $(KHAJE_BOARDS) $(KHAJE_BASE_DTB)
|
||||
dtb-y += $(bengal-dtb-y)
|
||||
|
||||
KONA_BASE_DTB += kona-iot.dtb kona-iot-v2.dtb kona-iot-v2.1.dtb
|
||||
|
||||
KONA_BOARDS += \
|
||||
kona-iot-v2.1-vc-overlay.dtbo
|
||||
|
||||
kona-dtb-$(CONFIG_ARCH_KONA) += \
|
||||
$(call add-overlays, $(KONA_BOARDS) ,$(KONA_BASE_DTB))
|
||||
kona-overlays-dtb-$(CONFIG_ARCH_KONA) += $(KONA_BOARDS) $(KONA_BASE_DTB)
|
||||
dtb-y += $(kona-dtb-y)
|
||||
|
||||
MONACO_BASE_DTB += monaco.dtb monacop.dtb
|
||||
|
||||
MONACO_BOARDS += \
|
||||
|
||||
@@ -28,7 +28,7 @@
|
||||
reg-names = "tpdm-base";
|
||||
|
||||
atid = <71>;
|
||||
coresight-name = "coresight-tpdm-swao_prio1";
|
||||
coresight-name = "coresight-tpdm-swao-prio-1";
|
||||
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
@@ -49,7 +49,7 @@
|
||||
reg = <0x10b0b000 0x1000>;
|
||||
reg-names = "tpdm-base";
|
||||
|
||||
coresight-name = "coresight-tpdm-swao_prio2";
|
||||
coresight-name = "coresight-tpdm-swao-prio-2";
|
||||
atid = <71>;
|
||||
clocks = <&aoss_qmp>;
|
||||
clock-names = "apb_pclk";
|
||||
@@ -70,7 +70,7 @@
|
||||
reg = <0x10b0c000 0x1000>;
|
||||
reg-names = "tpdm-base";
|
||||
|
||||
coresight-name = "coresight-tpdm-swao_prio3";
|
||||
coresight-name = "coresight-tpdm-swao-prio-3";
|
||||
|
||||
atid = <71>;
|
||||
clocks = <&aoss_qmp>;
|
||||
|
||||
103
qcom/cinder.dtsi
103
qcom/cinder.dtsi
@@ -1323,14 +1323,16 @@
|
||||
qcom,sriov-mask = <0x1E0>;
|
||||
|
||||
qcom,phy-init = <0x9040 0x01 0x0
|
||||
0x8030 0x0a 0x0
|
||||
0x80b4 0x88 0x0
|
||||
0x80c4 0x00 0x0
|
||||
0x80c8 0x1f 0x0
|
||||
0x80d4 0x12 0x0
|
||||
0x80d8 0x1a 0x0
|
||||
0x80dc 0xba 0x0
|
||||
0x80e0 0x8a 0x0
|
||||
0x80d4 0x93 0x0
|
||||
0x80d8 0xda 0x0
|
||||
0x80dc 0xf1 0x0
|
||||
0x80e0 0xca 0x0
|
||||
0x80e4 0x8b 0x0
|
||||
0x80e8 0x82 0x0
|
||||
0x80e8 0x81 0x0
|
||||
0x80ec 0x65 0x0
|
||||
0x80f0 0x1f 0x0
|
||||
0x80f4 0x1f 0x0
|
||||
@@ -1344,13 +1346,14 @@
|
||||
0x880c 0x02 0x0
|
||||
0x8844 0x1c 0x0
|
||||
0x884c 0x07 0x0
|
||||
0x8858 0x0f 0x0
|
||||
0x8874 0x28 0x0
|
||||
0x8878 0x28 0x0
|
||||
0x887c 0x0d 0x0
|
||||
0x8880 0x0d 0x0
|
||||
0x8858 0x1f 0x0
|
||||
0x8860 0x10 0x0
|
||||
0x8874 0x27 0x0
|
||||
0x8878 0x0a 0x0
|
||||
0x887c 0x17 0x0
|
||||
0x8880 0x19 0x0
|
||||
0x8884 0x00 0x0
|
||||
0x8888 0x00 0x0
|
||||
0x8888 0x03 0x0
|
||||
0x8894 0x00 0x0
|
||||
0x88a4 0x46 0x0
|
||||
0x88a8 0x04 0x0
|
||||
@@ -1358,64 +1361,79 @@
|
||||
0x88b0 0x04 0x0
|
||||
0x88b4 0xff 0x0
|
||||
0x88b8 0x04 0x0
|
||||
0x88bc 0x32 0x0
|
||||
0x88bc 0x19 0x0
|
||||
0x88c4 0x28 0x0
|
||||
0x88ec 0xfb 0x0
|
||||
0x88f0 0x03 0x0
|
||||
0x88f4 0xfb 0x0
|
||||
0x88f8 0x03 0x0
|
||||
0x88f8 0x01 0x0
|
||||
0x890c 0x02 0x0
|
||||
0x8958 0x13 0x0
|
||||
0x8958 0x12 0x0
|
||||
0x895c 0x00 0x0
|
||||
0x8968 0x0a 0x0
|
||||
0x896c 0x08 0x0
|
||||
0x8974 0x20 0x0
|
||||
0x897c 0x16 0x0
|
||||
0x897c 0x06 0x0
|
||||
0x899c 0x88 0x0
|
||||
0x89a0 0x14 0x0
|
||||
0x89a8 0x0f 0x0
|
||||
0x917c 0x2e 0x0
|
||||
0x9194 0x66 0x0
|
||||
0x9194 0x00 0x0
|
||||
0x91bc 0x11 0x0
|
||||
0x91f8 0x16 0x0
|
||||
0x91f8 0x00 0x0
|
||||
0x91fc 0x22 0x0
|
||||
0x9858 0x02 0x0
|
||||
0x988c 0x08 0x0
|
||||
0x98a8 0x16 0x0
|
||||
0x98ac 0x6b 0x0
|
||||
0x9910 0x02 0x0
|
||||
0x9964 0x2e 0x0
|
||||
0x9984 0x03 0x0
|
||||
0x998c 0x28 0x0
|
||||
0x999c 0x03 0x0
|
||||
0xe030 0x00 0x0
|
||||
0xe034 0x00 0x0
|
||||
0x999c 0x1f 0x0
|
||||
0x90c8 0xff 0x0
|
||||
0x90cc 0x8f 0x0
|
||||
0x91c4 0x00 0x0
|
||||
0x91c8 0x80 0x0
|
||||
0xe030 0x1d 0x0
|
||||
0xe034 0x0a 0x0
|
||||
0xe078 0x01 0x0
|
||||
0xe07c 0x80 0x0
|
||||
0xe080 0x50 0x0
|
||||
0xe208 0x0a 0x0
|
||||
0xe20c 0x0a 0x0
|
||||
0xe07c 0x00 0x0
|
||||
0xe080 0x70 0x0
|
||||
0xe208 0x0c 0x0
|
||||
0xe20c 0x08 0x0
|
||||
0xe218 0x04 0x0
|
||||
0xe21c 0x05 0x0
|
||||
0xe220 0x16 0x0
|
||||
0xe234 0x00 0x0
|
||||
0xe2b4 0x05 0x0
|
||||
0xe2e8 0x0a 0x0
|
||||
0xe30c 0x0d 0x0
|
||||
0xe2a0 0x00 0x0
|
||||
0xe2b0 0x00 0x0
|
||||
0xe2b4 0x45 0x0
|
||||
0xe2e0 0x00 0x0
|
||||
0xe2e8 0x03 0x0
|
||||
0xe2f4 0x30 0x0
|
||||
0xe30c 0x09 0x0
|
||||
0xe320 0x0b 0x0
|
||||
0xe348 0x1c 0x0
|
||||
0xe33c 0x7c 0x0
|
||||
0xe348 0xdc 0x0
|
||||
0xe34c 0x03 0x0
|
||||
0xe354 0x14 0x0
|
||||
0xe388 0x20 0x0
|
||||
0xe394 0x38 0x0
|
||||
0xe3f4 0x12 0x0
|
||||
0xe3f8 0x1a 0x0
|
||||
0xe3fc 0xba 0x0
|
||||
0xe400 0xca 0x0
|
||||
0xe404 0x8b 0x0
|
||||
0xe408 0x82 0x0
|
||||
0xe40c 0xef 0x0
|
||||
0xe410 0x2c 0x0
|
||||
0xe414 0x5b 0x0
|
||||
0xe418 0x7c 0x0
|
||||
0xe41c 0xeb 0x0
|
||||
0xe420 0x4b 0x0
|
||||
0xe424 0x86 0x0
|
||||
0xe3dc 0x07 0x0
|
||||
0xe3f4 0x9c 0x0
|
||||
0xe3f8 0x1b 0x0
|
||||
0xe3fc 0x3a 0x0
|
||||
0xe400 0xe3 0x0
|
||||
0xe404 0xbf 0x0
|
||||
0xe408 0x03 0x0
|
||||
0xe40c 0x8d 0x0
|
||||
0xe410 0x9b 0x0
|
||||
0xe414 0x1b 0x0
|
||||
0xe418 0x2d 0x0
|
||||
0xe41c 0xc7 0x0
|
||||
0xe420 0x5f 0x0
|
||||
0xe424 0x6e 0x0
|
||||
0xe428 0xff 0x0
|
||||
0x9000 0x00 0x0
|
||||
0x9044 0x03 0x0>;
|
||||
@@ -1523,7 +1541,8 @@
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
clocks = <&ecpricc ECPRI_CC_ECPRI_DMA_NOC_CLK>,
|
||||
<&ecpricc ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK>;
|
||||
<&ecpricc ECPRI_CC_ECPRI_FAST_DIV2_NOC_CLK>,
|
||||
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>;
|
||||
};
|
||||
|
||||
gem_noc: interconnect@19100000 {
|
||||
|
||||
@@ -1,3 +1,22 @@
|
||||
&reserved_memory {
|
||||
secure_display_memory: secure_display_region {
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0x0a000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&qcom_dma_heaps {
|
||||
qcom,display {
|
||||
qcom,dma-heap-name = "qcom,display";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
|
||||
qcom,max-align = <9>;
|
||||
memory-region = <&secure_display_memory>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
};
|
||||
|
||||
|
||||
@@ -5,3 +5,115 @@
|
||||
qcom,msm-name = "SA_DIREWOLF_IVI";
|
||||
qcom,msm-id = <460 0x10000>;
|
||||
};
|
||||
|
||||
®ulator {
|
||||
virt_regulator {
|
||||
compatible = "virtio,device31";
|
||||
|
||||
gcc_usb30_prim_gdsc: gcc_usb30_prim_gdsc {
|
||||
regulator-name = "gcc_usb30_prim_gdsc";
|
||||
};
|
||||
|
||||
gcc_usb30_sec_gdsc: gcc_usb30_sec_gdsc {
|
||||
regulator-name = "gcc_usb30_sec_gdsc";
|
||||
};
|
||||
|
||||
gcc_usb30_mp_gdsc: gcc_usb30_mp_gdsc {
|
||||
regulator-name = "gcc_usb30_mp_gdsc";
|
||||
};
|
||||
|
||||
gcc_pcie_2a_gdsc: gcc_pcie_2a_gdsc {
|
||||
regulator-name = "gcc_pcie_2a_gdsc";
|
||||
};
|
||||
|
||||
gcc_pcie_2b_gdsc: gcc_pcie_2b_gdsc {
|
||||
regulator-name = "gcc_pcie_2b_gdsc";
|
||||
};
|
||||
|
||||
gcc_pcie_3a_gdsc: gcc_pcie_3a_gdsc {
|
||||
regulator-name = "gcc_pcie_3a_gdsc";
|
||||
};
|
||||
|
||||
gcc_pcie_3b_gdsc: gcc_pcie_3b_gdsc {
|
||||
regulator-name = "gcc_pcie_3b_gdsc";
|
||||
};
|
||||
|
||||
gcc_pcie_4_gdsc: gcc_pcie_4_gdsc {
|
||||
regulator-name = "gcc_pcie_4_gdsc";
|
||||
};
|
||||
|
||||
L3A0: pm8540_a0_l3: regulator-pm8540_a0-l3 {
|
||||
regulator-name = "ldoa3";
|
||||
regulator-min-microvolt = <1140000>;
|
||||
regulator-max-microvolt = <1260000>;
|
||||
};
|
||||
|
||||
S4E0: pm8540_e0_s4: regulator-pm8540_e0-s4 {
|
||||
regulator-name = "smpe4";
|
||||
regulator-min-microvolt = <320000>;
|
||||
regulator-max-microvolt = <2040000>;
|
||||
};
|
||||
|
||||
L5A0: pm8540_a0_l5: regulator-pm8540_a0-l5 {
|
||||
regulator-name = "ldoa5";
|
||||
regulator-min-microvolt = <720000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
};
|
||||
|
||||
L6G0: pm8540_g0_l6: regulator-pm8540_g0-l6 {
|
||||
regulator-name = "ldog6";
|
||||
};
|
||||
|
||||
L7A0: pm8540_a0_l7: regulator-pm8540_a0-l7 {
|
||||
regulator-name = "ldoa7";
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <1980000>;
|
||||
};
|
||||
|
||||
L11A0: pm8540_a0_l11: regulator-pm8540_a0-l11 {
|
||||
regulator-name = "ldoa11";
|
||||
regulator-min-microvolt = <830000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
};
|
||||
|
||||
L13A0: pm8540_a0_l13: regulator-pm8540_a0-l13 {
|
||||
regulator-name = "ldoa13";
|
||||
regulator-min-microvolt = <2970000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
};
|
||||
|
||||
L1C0: pm8540_c0_l1: regulator-pm8540_c0-l1 {
|
||||
regulator-name = "ldoc1";
|
||||
regulator-min-microvolt = <720000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
};
|
||||
|
||||
L7C0: pm8540_c0_l7: regulator-pm8540_c0-l7 {
|
||||
regulator-name = "ldoc7";
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <1980000>;
|
||||
};
|
||||
|
||||
L2C0: pm8540_c0_l2: regulator-pm8540_c0-l2 {
|
||||
regulator-name = "ldoc2";
|
||||
regulator-min-microvolt = <2970000>;
|
||||
regulator-max-microvolt = <3544000>;
|
||||
};
|
||||
|
||||
L15A0: pm8540_a0_l15: regulator-pm8540_a0-l15 {
|
||||
regulator-name = "ldoa15";
|
||||
};
|
||||
|
||||
L7G0: pm8540_g0_l7: regulator-pm8540_g0-l7 {
|
||||
regulator-name = "ldog7";
|
||||
regulator-min-microvolt = <1620000>;
|
||||
regulator-max-microvolt = <1980000>;
|
||||
};
|
||||
|
||||
L4C0: pm8540_c0_l4: regulator-pm8540_c0-l4 {
|
||||
regulator-name = "ldoc4";
|
||||
regulator-min-microvolt = <1140000>;
|
||||
regulator-max-microvolt = <1260000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -157,7 +157,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
cpu-1-6 {
|
||||
cpu-1-9 {
|
||||
trips {
|
||||
thermal-engine-config {
|
||||
temperature = <125000>;
|
||||
@@ -171,22 +171,33 @@
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
fan_cpu16_config0: fan-cpu16-config0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <5000>;
|
||||
fan_cpu19_config0: fan-cpu19-config0 {
|
||||
temperature = <85000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
fan_cpu19_config1: fan-cpu19-config1 {
|
||||
temperature = <90000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
fan_cdev_0 {
|
||||
trip = <&fan_cpu16_config0>;
|
||||
cooling-device = <&fancontroller 1 1>;
|
||||
trip = <&fan_cpu19_config0>;
|
||||
cooling-device = <&fancontroller 2 2>;
|
||||
};
|
||||
|
||||
fan_cdev_1 {
|
||||
trip = <&fan_cpu19_config1>;
|
||||
cooling-device = <&fancontroller 3 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu-1-7 {
|
||||
cpu-1-10 {
|
||||
trips {
|
||||
thermal-engine-config {
|
||||
temperature = <125000>;
|
||||
@@ -200,17 +211,28 @@
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
fan_cpu17_config0: fan-cpu17-config0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <5000>;
|
||||
fan_cpu1a_config0: fan-cpu1a-config0 {
|
||||
temperature = <85000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
fan_cpu1a_config1: fan-cpu1a-config1 {
|
||||
temperature = <90000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
fan_cdev_0 {
|
||||
trip = <&fan_cpu17_config0>;
|
||||
cooling-device = <&fancontroller 1 1>;
|
||||
trip = <&fan_cpu1a_config0>;
|
||||
cooling-device = <&fancontroller 2 2>;
|
||||
};
|
||||
|
||||
fan_cdev_1 {
|
||||
trip = <&fan_cpu1a_config1>;
|
||||
cooling-device = <&fancontroller 3 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -230,7 +252,13 @@
|
||||
};
|
||||
|
||||
fan_gpuss0_config0: fan-gpuss0-config0 {
|
||||
temperature = <95000>;
|
||||
temperature = <70000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
fan_gpuss0_config1: fan-gpuss0-config1 {
|
||||
temperature = <90000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
@@ -239,7 +267,12 @@
|
||||
cooling-maps {
|
||||
fan_cdev_0 {
|
||||
trip = <&fan_gpuss0_config0>;
|
||||
cooling-device = <&fancontroller 1 1>;
|
||||
cooling-device = <&fancontroller 3 3>;
|
||||
};
|
||||
|
||||
fan_cdev_1 {
|
||||
trip = <&fan_gpuss0_config1>;
|
||||
cooling-device = <&fancontroller 4 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -259,7 +292,13 @@
|
||||
};
|
||||
|
||||
fan_gpuss1_config0: fan-gpuss1-config0 {
|
||||
temperature = <95000>;
|
||||
temperature = <70000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
fan_gpuss1_config1: fan-gpuss1-config1 {
|
||||
temperature = <90000>;
|
||||
hysteresis = <0>;
|
||||
type = "passive";
|
||||
};
|
||||
@@ -268,7 +307,40 @@
|
||||
cooling-maps {
|
||||
fan_cdev_0 {
|
||||
trip = <&fan_gpuss1_config0>;
|
||||
cooling-device = <&fancontroller 1 1>;
|
||||
cooling-device = <&fancontroller 3 3>;
|
||||
};
|
||||
|
||||
fan_cdev_1 {
|
||||
trip = <&fan_gpuss1_config1>;
|
||||
cooling-device = <&fancontroller 4 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb-therm {
|
||||
trips {
|
||||
fan_thmbat0_config0: fan-thmbat0-config0 {
|
||||
temperature = <43000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
fan_thmbat1_config1: fan-thmbat1-config1 {
|
||||
temperature = <45000>;
|
||||
hysteresis = <3000>;
|
||||
type = "passive";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
fan_cdev_0 {
|
||||
trip = <&fan_thmbat0_config0>;
|
||||
cooling-device = <&fancontroller 3 3>;
|
||||
};
|
||||
|
||||
fan_cdev_1 {
|
||||
trip = <&fan_thmbat1_config1>;
|
||||
cooling-device = <&fancontroller 4 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -221,7 +221,7 @@
|
||||
compatible = "qcom,userspace-cooling-devices";
|
||||
|
||||
display_fps: display-fps {
|
||||
qcom,max-level = <4>;
|
||||
qcom,max-level = <16>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -645,6 +645,14 @@
|
||||
size = <0x0 0x1000000>;
|
||||
};
|
||||
|
||||
glink_contig_mem: glink_contig_region {
|
||||
compatible = "shared-dma-pool";
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
reusable;
|
||||
alignment = <0x0 0x400000>;
|
||||
size = <0x0 0x1000000>;
|
||||
};
|
||||
|
||||
ramoops_mem: ramoops_region {
|
||||
compatible = "ramoops";
|
||||
alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
|
||||
@@ -662,6 +670,12 @@
|
||||
size = <0x0 0x2000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
|
||||
kinfo_mem: debug_kinfo_region {
|
||||
alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
|
||||
size = <0x0 0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
@@ -2568,6 +2582,11 @@
|
||||
qcom,glinkpkt-ch-name = "DATA11";
|
||||
qcom,glinkpkt-dev-name = "smd11";
|
||||
};
|
||||
qcom,glinkpkt-btoip_control {
|
||||
qcom,glinkpkt-edge = "adsp";
|
||||
qcom,glinkpkt-ch-name = "bt_cp_ctrl";
|
||||
qcom,glinkpkt-dev-name = "bt_cp_ctrl";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,glink {
|
||||
@@ -2713,7 +2732,7 @@
|
||||
iommus = <&apps_smmu 0x1961 0x0000>,
|
||||
<&apps_smmu 0x0C01 0x0020>,
|
||||
<&apps_smmu 0x19C1 0x0010>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2724,7 +2743,7 @@
|
||||
iommus = <&apps_smmu 0x1962 0x0000>,
|
||||
<&apps_smmu 0x0C02 0x0020>,
|
||||
<&apps_smmu 0x19C2 0x0010>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2735,7 +2754,7 @@
|
||||
iommus = <&apps_smmu 0x1963 0x0000>,
|
||||
<&apps_smmu 0x0C03 0x0020>,
|
||||
<&apps_smmu 0x19C3 0x0010>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2746,7 +2765,7 @@
|
||||
iommus = <&apps_smmu 0x1964 0x0000>,
|
||||
<&apps_smmu 0x0C04 0x0020>,
|
||||
<&apps_smmu 0x19C4 0x0010>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2757,7 +2776,7 @@
|
||||
iommus = <&apps_smmu 0x1965 0x0000>,
|
||||
<&apps_smmu 0x0C05 0x0020>,
|
||||
<&apps_smmu 0x19C5 0x0010>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2768,7 +2787,7 @@
|
||||
iommus = <&apps_smmu 0x1966 0x0000>,
|
||||
<&apps_smmu 0x0C06 0x0020>,
|
||||
<&apps_smmu 0x19C6 0x0010>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2779,7 +2798,7 @@
|
||||
iommus = <&apps_smmu 0x1967 0x0000>,
|
||||
<&apps_smmu 0x0C07 0x0020>,
|
||||
<&apps_smmu 0x19C7 0x0010>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2790,7 +2809,7 @@
|
||||
iommus = <&apps_smmu 0x1968 0x0000>,
|
||||
<&apps_smmu 0x0C08 0x0020>,
|
||||
<&apps_smmu 0x19C8 0x0010>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2802,7 +2821,7 @@
|
||||
iommus = <&apps_smmu 0x1969 0x0000>,
|
||||
<&apps_smmu 0x0C09 0x0020>,
|
||||
<&apps_smmu 0x19C9 0x0010>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x40000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
|
||||
dma-coherent;
|
||||
@@ -2813,7 +2832,7 @@
|
||||
label = "adsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1003 0x0080>,
|
||||
<&apps_smmu 0x1063 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2823,7 +2842,7 @@
|
||||
label = "adsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1004 0x0080>,
|
||||
<&apps_smmu 0x1064 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2833,7 +2852,7 @@
|
||||
label = "adsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1005 0x0080>,
|
||||
<&apps_smmu 0x1065 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
shared-cb = <8>;
|
||||
dma-coherent;
|
||||
@@ -2844,7 +2863,7 @@
|
||||
label = "adsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1006 0x0080>,
|
||||
<&apps_smmu 0x1066 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2854,7 +2873,7 @@
|
||||
label = "adsprpc-smd";
|
||||
iommus = <&apps_smmu 0x1007 0x0080>,
|
||||
<&apps_smmu 0x1067 0x0000>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2865,7 +2884,7 @@
|
||||
iommus = <&apps_smmu 0x196C 0x0000>,
|
||||
<&apps_smmu 0x0C0C 0x0020>,
|
||||
<&apps_smmu 0x19CC 0x0010>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2876,7 +2895,7 @@
|
||||
iommus = <&apps_smmu 0x196D 0x0000>,
|
||||
<&apps_smmu 0x0C0D 0x0020>,
|
||||
<&apps_smmu 0x19CD 0x0010>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2887,7 +2906,7 @@
|
||||
iommus = <&apps_smmu 0x196E 0x0000>,
|
||||
<&apps_smmu 0x0C0E 0x0020>,
|
||||
<&apps_smmu 0x19CE 0x0010>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -2898,7 +2917,7 @@
|
||||
iommus = <&apps_smmu 0x196F 0x0000>,
|
||||
<&apps_smmu 0x0C0F 0x0020>,
|
||||
<&apps_smmu 0x19CF 0x0010>;
|
||||
qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
|
||||
qcom,iommu-dma-addr-pool = <0x60000000 0x98000000>;
|
||||
qcom,iommu-faults = "stall-disable", "HUPCF";
|
||||
dma-coherent;
|
||||
};
|
||||
@@ -3859,6 +3878,11 @@
|
||||
};
|
||||
|
||||
msm_gpu: qcom,kgsl-3d0@3d00000 { };
|
||||
|
||||
google,debug-kinfo {
|
||||
compatible = "google,debug-kinfo";
|
||||
memory-region = <&kinfo_mem>;
|
||||
};
|
||||
};
|
||||
|
||||
&firmware {
|
||||
|
||||
@@ -2129,6 +2129,7 @@
|
||||
qcom,chd_silver {
|
||||
compatible = "qcom,core-hang-detect";
|
||||
label = "silver";
|
||||
cluster-id = <0>;
|
||||
qcom,threshold-arr = <0x0f1880b0 0x0f1980b0
|
||||
0x0f1a80b0 0x0f1b80b0>;
|
||||
qcom,config-arr = <0x0f1880b8 0x0f1980b8
|
||||
@@ -2138,6 +2139,7 @@
|
||||
qcom,chd_gold {
|
||||
compatible = "qcom,core-hang-detect";
|
||||
label = "gold";
|
||||
cluster-id = <1>;
|
||||
qcom,threshold-arr = <0x0f0880b0 0x0f0980b0
|
||||
0x0f0a80b0 0x0f0b80b0>;
|
||||
qcom,config-arr = <0x0f0880b8 0x0f0980b8
|
||||
|
||||
10
qcom/kona-iot-v2.1-vc-overlay.dts
Normal file
10
qcom/kona-iot-v2.1-vc-overlay.dts
Normal file
@@ -0,0 +1,10 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "kona-iot-v2.1-vc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. kona-iot VC";
|
||||
compatible = "qcom,kona-iot";
|
||||
qcom,board-id = <0x010020 0x07>;
|
||||
};
|
||||
1
qcom/kona-iot-v2.1-vc.dtsi
Normal file
1
qcom/kona-iot-v2.1-vc.dtsi
Normal file
@@ -0,0 +1 @@
|
||||
#include "kona-iot-vc.dtsi"
|
||||
9
qcom/kona-iot-v2.1.dts
Normal file
9
qcom/kona-iot-v2.1.dts
Normal file
@@ -0,0 +1,9 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "kona-iot-v2.1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. kona-iot v2.1 SoC";
|
||||
compatible = "qcom,kona-iot";
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
7
qcom/kona-iot-v2.1.dtsi
Normal file
7
qcom/kona-iot-v2.1.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
#include "kona-v2.1.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. kona-iot v2.1";
|
||||
compatible = "qcom,kona-iot";
|
||||
qcom,msm-id = <481 0x20001>;
|
||||
};
|
||||
9
qcom/kona-iot-v2.dts
Normal file
9
qcom/kona-iot-v2.dts
Normal file
@@ -0,0 +1,9 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "kona-iot-v2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. kona-iot v2 SoC";
|
||||
compatible = "qcom,kona-iot";
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
8
qcom/kona-iot-v2.dtsi
Normal file
8
qcom/kona-iot-v2.dtsi
Normal file
@@ -0,0 +1,8 @@
|
||||
#include "kona-v2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. kona-iot v2";
|
||||
compatible = "qcom,kona-iot";
|
||||
qcom,msm-id = <481 0x20000>;
|
||||
};
|
||||
|
||||
12
qcom/kona-iot-vc.dtsi
Normal file
12
qcom/kona-iot-vc.dtsi
Normal file
@@ -0,0 +1,12 @@
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
&tlmm {
|
||||
key_factory_reset {
|
||||
key_factory_reset_default: key_factory_reset_default {
|
||||
pins = "gpio22";
|
||||
function = "normal";
|
||||
input-enable;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
9
qcom/kona-iot.dts
Normal file
9
qcom/kona-iot.dts
Normal file
@@ -0,0 +1,9 @@
|
||||
/dts-v1/;
|
||||
|
||||
#include "kona-iot.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. kona-iot";
|
||||
compatible = "qcom,kona-iot";
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
7
qcom/kona-iot.dtsi
Normal file
7
qcom/kona-iot.dtsi
Normal file
@@ -0,0 +1,7 @@
|
||||
#include "kona.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kona-iot";
|
||||
compatible = "qcom,kona-iot";
|
||||
qcom,msm-id = <481 0x0>;
|
||||
};
|
||||
4462
qcom/kona-pinctrl.dtsi
Normal file
4462
qcom/kona-pinctrl.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
937
qcom/kona-regulators.dtsi
Normal file
937
qcom/kona-regulators.dtsi
Normal file
@@ -0,0 +1,937 @@
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
|
||||
/* RPMh regulators */
|
||||
&apps_rsc_drv2 {
|
||||
/* PM8150A S3 = VDD_MX supply */
|
||||
rpmh-regulator-mxlvl {
|
||||
compatible = "qcom,rpmh-arc-regulator";
|
||||
qcom,resource-name = "mx.lvl";
|
||||
proxy-supply = <&VDD_MX_LEVEL>;
|
||||
|
||||
VDD_MX_LEVEL: S3C_LEVEL:
|
||||
pm8150a_s3_level: regulator-pm8150a-s3-level {
|
||||
regulator-name = "pm8150a_s3_level";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,init-voltage-level =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
};
|
||||
|
||||
VDD_MX_LEVEL_AO: S3C_LEVEL_AO:
|
||||
pm8150a_s3_level_ao: regulator-pm8150a-s3-level-ao {
|
||||
regulator-name = "pm8150a_s3_level_ao";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,init-voltage-level =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
};
|
||||
|
||||
VDD_MX_MMCX_SUPPLY_LEVEL: regulator-pm8150a-s3-mmcx-sup-level {
|
||||
regulator-name = "pm8150a_s3_mmcx_sup_level";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
pm8150a_s3_mmcx_sup_level-parent-supply =
|
||||
<&VDD_CX_MMCX_SUPPLY_LEVEL>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,init-voltage-level =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PM8150 S3 + S2 + S1 = VDD_CX supply */
|
||||
rpmh-regulator-cxlvl {
|
||||
compatible = "qcom,rpmh-arc-regulator";
|
||||
qcom,resource-name = "cx.lvl";
|
||||
proxy-supply = <&VDD_CX_MMCX_SUPPLY_LEVEL>;
|
||||
|
||||
VDD_CX_LEVEL: S3A_LEVEL:
|
||||
pm8150_s3_level: regulator-pm8150-s3-level {
|
||||
regulator-name = "pm8150_s3_level";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
pm8150_s3_level-parent-supply = <&VDD_MX_LEVEL>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,init-voltage-level =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,min-dropout-voltage-level = <(-1)>;
|
||||
};
|
||||
|
||||
VDD_CX_LEVEL_AO: S3A_LEVEL_AO:
|
||||
pm8150_s3_level_ao: regulator-pm8150-s3-level-ao {
|
||||
regulator-name = "pm8150_s3_level_ao";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
|
||||
pm8150_s3_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,init-voltage-level =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
qcom,min-dropout-voltage-level = <(-1)>;
|
||||
};
|
||||
|
||||
VDD_CX_MMCX_SUPPLY_LEVEL: regulator-pm8150-s3-mmcx-sup-level {
|
||||
regulator-name = "pm8150_s3_mmcx_sup_level";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
||||
regulator-max-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,init-voltage-level =
|
||||
<RPMH_REGULATOR_LEVEL_MIN_SVS>;
|
||||
qcom,proxy-consumer-enable;
|
||||
qcom,proxy-consumer-voltage
|
||||
= <RPMH_REGULATOR_LEVEL_TURBO
|
||||
RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-smpa4 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "smpa4";
|
||||
S4A: pm8150_s4: regulator-pm8150-s4 {
|
||||
regulator-name = "pm8150_s4";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1920000>;
|
||||
qcom,init-voltage = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-smpa5 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "smpa5";
|
||||
S5A: pm8150_s5: regulator-pm8150-s5 {
|
||||
regulator-name = "pm8150_s5";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1824000>;
|
||||
regulator-max-microvolt = <2040000>;
|
||||
qcom,init-voltage = <1824000>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-smpa6 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "smpa6";
|
||||
S6A: pm8150_s6: regulator-pm8150-s6 {
|
||||
regulator-name = "pm8150_s6";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1128000>;
|
||||
qcom,init-voltage = <600000>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa2 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa2";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L2A: pm8150_l2: regulator-pm8150-l2 {
|
||||
regulator-name = "pm8150_l2";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <3072000>;
|
||||
regulator-max-microvolt = <3072000>;
|
||||
qcom,init-voltage = <3072000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa3 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa3";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 30000>;
|
||||
L3A: pm8150_l3: regulator-pm8150-l3 {
|
||||
regulator-name = "pm8150_l3";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <928000>;
|
||||
regulator-max-microvolt = <932000>;
|
||||
qcom,init-voltage = <928000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PM8150 L4 = VDD_SSC_MX supply */
|
||||
rpmh-regulator-lmxlvl {
|
||||
compatible = "qcom,rpmh-arc-regulator";
|
||||
qcom,resource-name = "lmx.lvl";
|
||||
L4A_LEVEL: pm8150_l4_level: regulator-pm8150-l4-level {
|
||||
regulator-name = "pm8150_l4_level";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt =
|
||||
<RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,init-voltage-level
|
||||
= <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa5 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa5";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 30000>;
|
||||
proxy-supply = <&pm8150_l5>;
|
||||
L5A: pm8150_l5: regulator-pm8150-l5 {
|
||||
regulator-name = "pm8150_l5";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
qcom,init-voltage = <880000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,proxy-consumer-enable;
|
||||
qcom,proxy-consumer-current = <100000>;
|
||||
};
|
||||
|
||||
L5A_AO: pm8150_l5_ao: regulator-pm8150-l5-ao {
|
||||
regulator-name = "pm8150_l5_ao";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
qcom,init-voltage = <880000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
regulator-pm8150-l5-so {
|
||||
regulator-name = "pm8150_l5_so";
|
||||
qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <880000>;
|
||||
qcom,init-voltage = <880000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
qcom,init-enable = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa6 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa6";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 30000>;
|
||||
L6A: pm8150_l6: regulator-pm8150-l6 {
|
||||
regulator-name = "pm8150_l6";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
qcom,init-voltage = <1200000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa7 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa7";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L7A: pm8150_l7: regulator-pm8150-l7 {
|
||||
regulator-name = "pm8150_l7";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1704000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,init-voltage = <1704000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa9 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa9";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 30000>;
|
||||
proxy-supply = <&pm8150_l9>;
|
||||
L9A: pm8150_l9: regulator-pm8150-l9 {
|
||||
regulator-name = "pm8150_l9";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
qcom,init-voltage = <1200000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,proxy-consumer-enable;
|
||||
qcom,proxy-consumer-current = <100000>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa10 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa10";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L10A: pm8150_l10: regulator-pm8150-l10 {
|
||||
regulator-name = "pm8150_l10";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
qcom,init-voltage = <1800000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PM8150 L11 = VDD_SSC_CX supply */
|
||||
rpmh-regulator-lcxlvl {
|
||||
compatible = "qcom,rpmh-arc-regulator";
|
||||
qcom,resource-name = "lcx.lvl";
|
||||
L11A_LEVEL: pm8150_l11_level: regulator-pm8150-l11-level {
|
||||
regulator-name = "pm8150_l11_level";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,init-voltage-level
|
||||
= <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa12 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa12";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L12A: pm8150_l12: regulator-pm8150-l12 {
|
||||
regulator-name = "pm8150_l12";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,init-voltage = <1800000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
L12A_AO: pm8150_l12_ao: regulator-pm8150-l12-ao {
|
||||
regulator-name = "pm8150_l12_ao";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,init-voltage = <1800000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
|
||||
regulator-pm8150-l12-so {
|
||||
regulator-name = "pm8150_l12_so";
|
||||
qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,init-voltage = <1800000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
qcom,init-enable = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa13 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa13";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L13A: pm8150_l13: regulator-pm8150-l13 {
|
||||
regulator-name = "pm8150_l13";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
qcom,init-voltage = <3008000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa14 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa14";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
proxy-supply = <&pm8150_l14>;
|
||||
L14A: pm8150_l14: regulator-pm8150-l14 {
|
||||
regulator-name = "pm8150_l14";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
qcom,proxy-consumer-enable;
|
||||
qcom,proxy-consumer-current = <62000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1880000>;
|
||||
qcom,init-voltage = <1800000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa15 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa15";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L15A: pm8150_l15: regulator-pm8150-l15 {
|
||||
regulator-name = "pm8150_l15";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,init-voltage = <1800000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa16 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa16";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L16A: pm8150_l16: regulator-pm8150-l16 {
|
||||
regulator-name = "pm8150_l16";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <3024000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
qcom,init-voltage = <3024000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa17 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa17";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L17A: pm8150_l17: regulator-pm8150-l17 {
|
||||
regulator-name = "pm8150_l17";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <2496000>;
|
||||
regulator-max-microvolt = <3008000>;
|
||||
qcom,init-voltage = <2496000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoa18 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoa18";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 30000>;
|
||||
L18A: pm8150_l18: regulator-pm8150-l18 {
|
||||
regulator-name = "pm8150_l18";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
qcom,init-voltage = <800000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PM8150A S1 + S2 = VDD_GFX supply */
|
||||
rpmh-regulator-gfxlvl {
|
||||
compatible = "qcom,rpmh-arc-regulator";
|
||||
qcom,resource-name = "gfx.lvl";
|
||||
VDD_GFX_LEVEL: S1C_LEVEL:
|
||||
pm8150a_s1_level: regulator-pm8150a-s1-level {
|
||||
regulator-name = "pm8150a_s1_level";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,init-voltage-level
|
||||
= <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PM8150A S4 + S5 = VDD_MMCX supply */
|
||||
rpmh-regulator-mmcxlvl {
|
||||
compatible = "qcom,rpmh-arc-regulator";
|
||||
qcom,resource-name = "mmcx.lvl";
|
||||
proxy-supply = <&VDD_MMCX_LEVEL>;
|
||||
|
||||
VDD_MMCX_LEVEL: S4C_LEVEL:
|
||||
pm8150a_s4_level: regulator-pm8150a-s4-level {
|
||||
regulator-name = "pm8150a_s4_level";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
pm8150a_s4_level-parent-supply = <&VDD_MX_MMCX_SUPPLY_LEVEL>;
|
||||
regulator-min-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
regulator-max-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,init-voltage-level
|
||||
= <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,min-dropout-voltage-level = <(-1)>;
|
||||
qcom,proxy-consumer-enable;
|
||||
qcom,proxy-consumer-voltage
|
||||
= <RPMH_REGULATOR_LEVEL_TURBO
|
||||
RPMH_REGULATOR_LEVEL_MAX>;
|
||||
};
|
||||
|
||||
VDD_MMCX_LEVEL_AO: S4C_LEVEL_AO:
|
||||
pm8150a_s4_level_ao: regulator-pm8150a-s4-level-ao {
|
||||
regulator-name = "pm8150a_s4_level_ao";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
|
||||
pm8150a_s4_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>;
|
||||
regulator-min-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
regulator-max-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,init-voltage-level
|
||||
= <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
qcom,min-dropout-voltage-level = <(-1)>;
|
||||
};
|
||||
|
||||
regulator-pm8150a-s4-level-so {
|
||||
regulator-name = "pm8150a_s4_level_so";
|
||||
qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
|
||||
regulator-min-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
regulator-max-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,init-voltage-level
|
||||
= <RPMH_REGULATOR_LEVEL_LOW_SVS>;
|
||||
};
|
||||
};
|
||||
|
||||
/* PM8150A S6 = VDD_EBI supply */
|
||||
rpmh-regulator-ebilvl {
|
||||
compatible = "qcom,rpmh-arc-regulator";
|
||||
qcom,resource-name = "ebi.lvl";
|
||||
S6C_LEVEL: pm8150a_s6_level: regulator-pm8150a-s6-level {
|
||||
regulator-name = "pm8150a_s6_level";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
regulator-max-microvolt
|
||||
= <RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,init-voltage-level
|
||||
= <RPMH_REGULATOR_LEVEL_RETENTION>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-smpc7 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "smpc7";
|
||||
S7C: pm8150a_s7: regulator-pm8150a-s7 {
|
||||
regulator-name = "pm8150a_s7";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <348000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
qcom,init-voltage = <348000>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-smpc8 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "smpc8";
|
||||
qcom,regulator-type = "pmic5-hfsmps";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_RET
|
||||
RPMH_REGULATOR_MODE_AUTO>;
|
||||
qcom,mode-threshold-currents = <0 200000>;
|
||||
S8C: pm8150a_s8: regulator-pm8150a-s8 {
|
||||
regulator-name = "pm8150a_s8";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
qcom,init-voltage = <1200000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_RET>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoc1 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoc1";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
L1C: pm8150a_l1: regulator-pm8150a-l1 {
|
||||
regulator-name = "pm8150a_l1";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,init-voltage = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoc2 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoc2";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 30000>;
|
||||
L2C: pm8150a_l2: regulator-pm8150a-l2 {
|
||||
regulator-name = "pm8150a_l2";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1304000>;
|
||||
qcom,init-voltage = <1200000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoc3 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoc3";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 30000>;
|
||||
L3C: pm8150a_l3: regulator-pm8150a-l3 {
|
||||
regulator-name = "pm8150a_l3";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
qcom,init-voltage = <800000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoc4 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoc4";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L4C: pm8150a_l4: regulator-pm8150a-l4 {
|
||||
regulator-name = "pm8150a_l4";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
qcom,init-voltage = <1800000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoc5 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoc5";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L5C: pm8150a_l5: regulator-pm8150a-l5 {
|
||||
regulator-name = "pm8150a_l5";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
qcom,init-voltage = <1800000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoc6 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoc6";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L6C: pm8150a_l6: regulator-pm8150a-l6 {
|
||||
regulator-name = "pm8150a_l6";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
qcom,init-voltage = <1800000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoc7 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoc7";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L7C: pm8150a_l7: regulator-pm8150a-l7 {
|
||||
regulator-name = "pm8150a_l7";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <2856000>;
|
||||
regulator-max-microvolt = <3104000>;
|
||||
qcom,init-voltage = <2856000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoc8 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoc8";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
L8C: pm8150a_l8: regulator-pm8150a-l8 {
|
||||
regulator-name = "pm8150a_l8";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,init-voltage = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoc9 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoc9";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L9C: pm8150a_l9: regulator-pm8150a-l9 {
|
||||
regulator-name = "pm8150a_l9";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <2704000>;
|
||||
regulator-max-microvolt = <2960000>;
|
||||
qcom,init-voltage = <2704000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoc10 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoc10";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L10C: pm8150a_l10: regulator-pm8150a-l10 {
|
||||
regulator-name = "pm8150a_l10";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3312000>;
|
||||
qcom,init-voltage = <3000000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldoc11 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldoc11";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
proxy-supply = <&pm8150a_l11>;
|
||||
L11C: pm8150a_l11: regulator-pm8150a-l11 {
|
||||
regulator-name = "pm8150a_l11";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
qcom,proxy-consumer-enable;
|
||||
qcom,proxy-consumer-current = <857000>;
|
||||
regulator-min-microvolt = <3104000>;
|
||||
regulator-max-microvolt = <3304000>;
|
||||
qcom,init-voltage = <3104000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-bobc1 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "bobc1";
|
||||
qcom,regulator-type = "pmic5-bob";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_PASS
|
||||
RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 1000000 2000000>;
|
||||
qcom,send-defaults;
|
||||
|
||||
BOB: pm8150a_bob: regulator-pm8150a-bob {
|
||||
regulator-name = "pm8150a_bob";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3960000>;
|
||||
qcom,init-voltage = <3312000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_PASS>;
|
||||
};
|
||||
|
||||
BOB_AO: pm8150a_bob_ao: regulator-pm8150a-bob-ao {
|
||||
regulator-name = "pm8150a_bob_ao";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
|
||||
regulator-min-microvolt = <3008000>;
|
||||
regulator-max-microvolt = <3960000>;
|
||||
qcom,init-voltage = <3008000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_AUTO>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-smpf1 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "smpf1";
|
||||
S1F: pm8009_s1: regulator-pm8009-s1 {
|
||||
regulator-name = "pm8009_s1";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
qcom,init-voltage = <1200000>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-smpf2 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "smpf2";
|
||||
S2F: pm8009_s2: regulator-pm8009-s2 {
|
||||
regulator-name = "pm8009_s2";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <512000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
qcom,init-voltage = <512000>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldof1 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldof1";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 30000>;
|
||||
L1F: pm8009_l1: regulator-pm8009-l1 {
|
||||
regulator-name = "pm8009_l1";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1104000>;
|
||||
regulator-max-microvolt = <1104000>;
|
||||
qcom,init-voltage = <1104000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldof2 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldof2";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 30000>;
|
||||
L2F: pm8009_l2: regulator-pm8009-l2 {
|
||||
regulator-name = "pm8009_l2";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
qcom,init-voltage = <1200000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldof3 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldof3";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 30000>;
|
||||
L3F: pm8009_l3: regulator-pm8009-l3 {
|
||||
regulator-name = "pm8009_l3";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1056000>;
|
||||
regulator-max-microvolt = <1056000>;
|
||||
qcom,init-voltage = <1056000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldof5 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldof5";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L5F: pm8009_l5: regulator-pm8009-l5 {
|
||||
regulator-name = "pm8009_l5";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
qcom,init-voltage = <2800000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldof6 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldof6";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
qcom,supported-modes =
|
||||
<RPMH_REGULATOR_MODE_LPM
|
||||
RPMH_REGULATOR_MODE_HPM>;
|
||||
qcom,mode-threshold-currents = <0 10000>;
|
||||
L6F: pm8009_l6: regulator-pm8009-l6 {
|
||||
regulator-name = "pm8009_l6";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
qcom,init-voltage = <2800000>;
|
||||
qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
|
||||
};
|
||||
};
|
||||
|
||||
rpmh-regulator-ldof7 {
|
||||
compatible = "qcom,rpmh-vrm-regulator";
|
||||
qcom,resource-name = "ldof7";
|
||||
qcom,regulator-type = "pmic5-ldo";
|
||||
L7F: pm8009_l7: regulator-pm8009-l7 {
|
||||
regulator-name = "pm8009_l7";
|
||||
qcom,set = <RPMH_REGULATOR_SET_ALL>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,init-voltage = <1800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
refgen: refgen-regulator@88e7000 {
|
||||
compatible = "qcom,refgen-kona-regulator";
|
||||
reg = <0x88e7000 0x84>;
|
||||
regulator-name = "refgen";
|
||||
regulator-enable-ramp-delay = <5>;
|
||||
proxy-supply = <&refgen>;
|
||||
qcom,proxy-consumer-enable;
|
||||
};
|
||||
};
|
||||
8
qcom/kona-v2.1.dtsi
Normal file
8
qcom/kona-v2.1.dtsi
Normal file
@@ -0,0 +1,8 @@
|
||||
|
||||
#include "kona-v2.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. kona v2.1";
|
||||
compatible = "qcom,kona";
|
||||
qcom,msm-id = <356 0x20001>;
|
||||
};
|
||||
23
qcom/kona-v2.dtsi
Normal file
23
qcom/kona-v2.dtsi
Normal file
@@ -0,0 +1,23 @@
|
||||
#include "kona.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. kona v2";
|
||||
compatible = "qcom,kona";
|
||||
qcom,msm-id = <356 0x20000>;
|
||||
};
|
||||
|
||||
&CPU4 {
|
||||
dynamic-power-coefficient = <533>;
|
||||
};
|
||||
|
||||
&CPU5 {
|
||||
dynamic-power-coefficient = <533>;
|
||||
};
|
||||
|
||||
&CPU6 {
|
||||
dynamic-power-coefficient = <533>;
|
||||
};
|
||||
|
||||
&CPU7 {
|
||||
dynamic-power-coefficient = <642>;
|
||||
};
|
||||
1155
qcom/kona.dtsi
Normal file
1155
qcom/kona.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
156
qcom/lemans.dtsi
156
qcom/lemans.dtsi
@@ -8,6 +8,7 @@
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/soc/qcom,ipcc.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Lemans";
|
||||
@@ -908,6 +909,7 @@
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
mc_virt: interconnect@1 {
|
||||
@@ -915,6 +917,7 @@
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
config_noc: interconnect@014C0000 {
|
||||
@@ -923,6 +926,7 @@
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
system_noc: interconnect@01680000 {
|
||||
@@ -931,6 +935,7 @@
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
aggre1_noc:interconnect@016C0000 {
|
||||
@@ -939,6 +944,7 @@
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
|
||||
@@ -952,6 +958,7 @@
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
|
||||
<&rpmhcc RPMH_IPA_CLK>;
|
||||
};
|
||||
@@ -962,6 +969,7 @@
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
gpdsp_anoc: interconnect@01780000 {
|
||||
@@ -970,6 +978,7 @@
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
mmss_noc: interconnect@017A0000 {
|
||||
@@ -978,6 +987,7 @@
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
lpass_ag_noc: interconnect@03C40000 {
|
||||
@@ -986,6 +996,7 @@
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
dc_noc: interconnect@090E0000 {
|
||||
@@ -994,6 +1005,7 @@
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
gem_noc: interconnect@09100000 {
|
||||
@@ -1003,6 +1015,7 @@
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
nspa_noc: interconnect@260C0000 {
|
||||
@@ -1011,6 +1024,7 @@
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
nspb_noc: interconnect@2A0C0000 {
|
||||
@@ -1019,6 +1033,7 @@
|
||||
#interconnect-cells = <1>;
|
||||
qcom,bcm-voter-names = "hlos";
|
||||
qcom,bcm-voters = <&apps_bcm_voter>;
|
||||
qcom,skip-qos;
|
||||
};
|
||||
|
||||
vendor_hooks: qcom,cpu-vendor-hooks {
|
||||
@@ -1190,6 +1205,147 @@
|
||||
vote = <44>;
|
||||
};
|
||||
};
|
||||
|
||||
tcsr_mutex_block: syscon@1f40000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x1f40000 0x20000>;
|
||||
};
|
||||
|
||||
tcsr_mutex: hwlock@1f40000 {
|
||||
compatible = "qcom,tcsr-mutex";
|
||||
syscon = <&tcsr_mutex_block 0 0x1000>;
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
smem: qcom,smem {
|
||||
compatible = "qcom,smem";
|
||||
memory-region = <&smem_mem>;
|
||||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
|
||||
aoss_qmp: power-controller@c300000 {
|
||||
|
||||
compatible = "qcom,sm8150-aoss-qmp";
|
||||
reg = <0xc300000 0x400>;
|
||||
mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
|
||||
IPCC_MPROC_SIGNAL_GLINK_QMP>;
|
||||
mbox-names = "aop_qmp";
|
||||
interrupt-parent = <&ipcc_mproc>;
|
||||
interrupts = <IPCC_CLIENT_AOP
|
||||
IPCC_MPROC_SIGNAL_GLINK_QMP
|
||||
IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
#clock-cells = <0>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
qmp_aop: qcom,qmp-aop@c300000 {
|
||||
compatible = "qcom,qmp-mbox";
|
||||
qcom,qmp = <&aoss_qmp>;
|
||||
label = "aop";
|
||||
#mbox-cells = <1>;
|
||||
};
|
||||
|
||||
qcom,glinkpkt {
|
||||
compatible = "qcom,glinkpkt";
|
||||
|
||||
qcom,glinkpkt-apr-apps2 {
|
||||
qcom,glinkpkt-edge = "adsp";
|
||||
qcom,glinkpkt-ch-name = "apr_apps2";
|
||||
qcom,glinkpkt-dev-name = "apr_apps2";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,smp2p-adsp {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <443>, <429>;
|
||||
interrupt-parent = <&ipcc_mproc>;
|
||||
interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
|
||||
IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
|
||||
IPCC_MPROC_SIGNAL_SMP2P>;
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <2>;
|
||||
|
||||
adsp_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
adsp_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,smp2p-cdsp@1799000c {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <94>, <432>;
|
||||
interrupt-parent = <&ipcc_mproc>;
|
||||
interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
|
||||
IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <5>;
|
||||
|
||||
cdsp_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
cdsp_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,smp2p-gpdsp0 {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <617>, <616>;
|
||||
interrupt-parent = <&ipcc_mproc>;
|
||||
interrupts = <IPCC_CLIENT_GPDSP0 IPCC_MPROC_SIGNAL_SMP2P
|
||||
IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc_mproc IPCC_CLIENT_GPDSP0
|
||||
IPCC_MPROC_SIGNAL_SMP2P>;
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <17>;
|
||||
|
||||
gpdsp0_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
gpdsp0_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,smp2p-gpdsp1 {
|
||||
compatible = "qcom,smp2p";
|
||||
qcom,smem = <617>, <616>;
|
||||
interrupt-parent = <&ipcc_mproc>;
|
||||
interrupts = <IPCC_CLIENT_GPDSP1 IPCC_MPROC_SIGNAL_SMP2P
|
||||
IRQ_TYPE_EDGE_RISING>;
|
||||
mboxes = <&ipcc_mproc IPCC_CLIENT_GPDSP1
|
||||
IPCC_MPROC_SIGNAL_SMP2P>;
|
||||
qcom,local-pid = <0>;
|
||||
qcom,remote-pid = <18>;
|
||||
|
||||
gpdsp1_smp2p_out: master-kernel {
|
||||
qcom,entry-name = "master-kernel";
|
||||
#qcom,smem-state-cells = <1>;
|
||||
};
|
||||
|
||||
gpdsp1_smp2p_in: slave-kernel {
|
||||
qcom,entry-name = "slave-kernel";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "lemans-4pmic-regulators.dtsi"
|
||||
|
||||
@@ -21,5 +21,12 @@
|
||||
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
|
||||
memory-region = <&user_contig_mem>;
|
||||
};
|
||||
|
||||
qcom,display {
|
||||
qcom,dma-heap-name = "qcom,display";
|
||||
qcom,dma-heap-type = <HEAP_TYPE_CMA>;
|
||||
qcom,max-align = <9>;
|
||||
memory-region = <&non_secure_display_memory>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -13,7 +13,7 @@
|
||||
qupv3_se6_2uart_tx_active: qupv3_se6_2uart_tx_active {
|
||||
mux {
|
||||
pins = "gpio30";
|
||||
function = "qup0_l2";
|
||||
function = "qup06";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -23,10 +23,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se3_2uart_rx_active: qupv3_se3_2uart_rx_active {
|
||||
qupv3_se6_2uart_rx_active: qupv3_se6_2uart_rx_active {
|
||||
mux {
|
||||
pins = "gpio31";
|
||||
function = "qup0_l3";
|
||||
function = "qup06";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -54,7 +54,7 @@
|
||||
qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active {
|
||||
mux {
|
||||
pins = "gpio4";
|
||||
function = "qup0_l0";
|
||||
function = "qup00";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -67,7 +67,7 @@
|
||||
qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active {
|
||||
mux {
|
||||
pins = "gpio5";
|
||||
function = "qup0_l1";
|
||||
function = "qup00";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -157,7 +157,7 @@
|
||||
qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio4";
|
||||
function = "qup0_l0";
|
||||
function = "qup00";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -170,7 +170,7 @@
|
||||
qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active {
|
||||
mux {
|
||||
pins = "gpio5";
|
||||
function = "qup0_l1";
|
||||
function = "qup00";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -183,7 +183,7 @@
|
||||
qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active {
|
||||
mux {
|
||||
pins = "gpio6";
|
||||
function = "qup0_l2";
|
||||
function = "qup00";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -196,7 +196,7 @@
|
||||
qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active {
|
||||
mux {
|
||||
pins = "gpio7";
|
||||
function = "qup0_l3";
|
||||
function = "qup00";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -226,7 +226,7 @@
|
||||
qupv3_se1_i2c_sda_active: qupv3_se1_i2c_sda_active {
|
||||
mux {
|
||||
pins = "gpio10";
|
||||
function = "qup0_l0";
|
||||
function = "qup01";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -239,7 +239,7 @@
|
||||
qupv3_se1_i2c_scl_active: qupv3_se1_i2c_scl_active {
|
||||
mux {
|
||||
pins = "gpio11";
|
||||
function = "qup0_l1";
|
||||
function = "qup01";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -267,7 +267,7 @@
|
||||
qupv3_se1_spi_miso_active: qupv3_se1_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio10";
|
||||
function = "qup0_l0";
|
||||
function = "qup01";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -280,7 +280,7 @@
|
||||
qupv3_se1_spi_mosi_active: qupv3_se1_spi_mosi_active {
|
||||
mux {
|
||||
pins = "gpio11";
|
||||
function = "qup0_l1";
|
||||
function = "qup01";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -293,7 +293,7 @@
|
||||
qupv3_se1_spi_clk_active: qupv3_se1_spi_clk_active {
|
||||
mux {
|
||||
pins = "gpio12";
|
||||
function = "qup0_l2";
|
||||
function = "qup01";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -306,7 +306,7 @@
|
||||
qupv3_se1_spi_cs_active: qupv3_se1_spi_cs_active {
|
||||
mux {
|
||||
pins = "gpio13";
|
||||
function = "qup0_l3";
|
||||
function = "qup01";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -336,7 +336,7 @@
|
||||
qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active {
|
||||
mux {
|
||||
pins = "gpio0";
|
||||
function = "qup0_l0";
|
||||
function = "qup02";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -349,7 +349,7 @@
|
||||
qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active {
|
||||
mux {
|
||||
pins = "gpio1";
|
||||
function = "qup0_l1";
|
||||
function = "qup02";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -377,7 +377,7 @@
|
||||
qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio0";
|
||||
function = "qup0_l0";
|
||||
function = "qup02";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -390,7 +390,7 @@
|
||||
qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active {
|
||||
mux {
|
||||
pins = "gpio1";
|
||||
function = "qup0_l1";
|
||||
function = "qup02";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -403,7 +403,7 @@
|
||||
qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active {
|
||||
mux {
|
||||
pins = "gpio2";
|
||||
function = "qup0_l2";
|
||||
function = "qup02";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -416,7 +416,7 @@
|
||||
qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active {
|
||||
mux {
|
||||
pins = "gpio3";
|
||||
function = "qup0_l3";
|
||||
function = "qup02";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -446,7 +446,7 @@
|
||||
qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active {
|
||||
mux {
|
||||
pins = "gpio14";
|
||||
function = "qup0_l0";
|
||||
function = "qup03";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -459,7 +459,7 @@
|
||||
qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active {
|
||||
mux {
|
||||
pins = "gpio15";
|
||||
function = "qup0_l1";
|
||||
function = "qup03";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -487,7 +487,7 @@
|
||||
qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio14";
|
||||
function = "qup0_l0";
|
||||
function = "qup03";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -500,7 +500,7 @@
|
||||
qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active {
|
||||
mux {
|
||||
pins = "gpio15";
|
||||
function = "qup0_l1";
|
||||
function = "qup03";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -513,7 +513,7 @@
|
||||
qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active {
|
||||
mux {
|
||||
pins = "gpio16";
|
||||
function = "qup0_l2";
|
||||
function = "qup03";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -526,7 +526,7 @@
|
||||
qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active {
|
||||
mux {
|
||||
pins = "gpio17";
|
||||
function = "qup0_l3";
|
||||
function = "qup03";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -556,7 +556,7 @@
|
||||
qupv3_se4_i2c_sda_active: qupv3_se4_i2c_sda_active {
|
||||
mux {
|
||||
pins = "gpio20";
|
||||
function = "qup0_l0";
|
||||
function = "qup04";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -569,7 +569,7 @@
|
||||
qupv3_se4_i2c_scl_active: qupv3_se4_i2c_scl_active {
|
||||
mux {
|
||||
pins = "gpio21";
|
||||
function = "qup0_l1";
|
||||
function = "qup04";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -597,7 +597,7 @@
|
||||
qupv3_se4_spi_miso_active: qupv3_se4_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio20";
|
||||
function = "qup0_l0";
|
||||
function = "qup04";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -610,7 +610,7 @@
|
||||
qupv3_se4_spi_mosi_active: qupv3_se4_spi_mosi_active {
|
||||
mux {
|
||||
pins = "gpio21";
|
||||
function = "qup0_l1";
|
||||
function = "qup04";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -623,7 +623,7 @@
|
||||
qupv3_se4_spi_clk_active: qupv3_se4_spi_clk_active {
|
||||
mux {
|
||||
pins = "gpio22";
|
||||
function = "qup0_l2";
|
||||
function = "qup04";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -636,7 +636,7 @@
|
||||
qupv3_se4_spi_cs_active: qupv3_se4_spi_cs_active {
|
||||
mux {
|
||||
pins = "gpio23";
|
||||
function = "qup0_l3";
|
||||
function = "qup04";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -666,7 +666,7 @@
|
||||
qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active {
|
||||
mux {
|
||||
pins = "gpio26";
|
||||
function = "qup0_l0";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -679,7 +679,7 @@
|
||||
qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active {
|
||||
mux {
|
||||
pins = "gpio27";
|
||||
function = "qup0_l1";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -707,7 +707,7 @@
|
||||
qupv3_se5_spi_miso_active: qupv3_se5_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio26";
|
||||
function = "qup0_l0";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -720,7 +720,7 @@
|
||||
qupv3_se5_spi_mosi_active: qupv3_se5_spi_mosi_active {
|
||||
mux {
|
||||
pins = "gpio27";
|
||||
function = "qup0_l1";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -733,7 +733,7 @@
|
||||
qupv3_se5_spi_clk_active: qupv3_se5_spi_clk_active {
|
||||
mux {
|
||||
pins = "gpio28";
|
||||
function = "qup0_l2";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -746,7 +746,7 @@
|
||||
qupv3_se5_spi_cs_active: qupv3_se5_spi_cs_active {
|
||||
mux {
|
||||
pins = "gpio29";
|
||||
function = "qup0_l3";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -776,7 +776,7 @@
|
||||
qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active {
|
||||
mux {
|
||||
pins = "gpio24";
|
||||
function = "qup0_10";
|
||||
function = "qup06";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -789,7 +789,7 @@
|
||||
qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active {
|
||||
mux {
|
||||
pins = "gpio25";
|
||||
function = "qup0_11";
|
||||
function = "qup06";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -817,7 +817,7 @@
|
||||
qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active {
|
||||
mux {
|
||||
pins = "gpio24";
|
||||
function = "qup0_l0";
|
||||
function = "qup06";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -830,7 +830,7 @@
|
||||
qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active {
|
||||
mux {
|
||||
pins = "gpio25";
|
||||
function = "qup0_l1";
|
||||
function = "qup06";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -843,7 +843,7 @@
|
||||
qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active {
|
||||
mux {
|
||||
pins = "gpio30";
|
||||
function = "qup0_l2";
|
||||
function = "qup06";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -856,7 +856,7 @@
|
||||
qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active {
|
||||
mux {
|
||||
pins = "gpio31";
|
||||
function = "qup0_l3";
|
||||
function = "qup06";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -1158,7 +1158,7 @@
|
||||
qupv3_se5_cts: qupv3_se5_cts {
|
||||
mux {
|
||||
pins = "gpio26";
|
||||
function = "qup0_l0";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -1171,7 +1171,7 @@
|
||||
qupv3_se5_rts: qupv3_se5_rts {
|
||||
mux {
|
||||
pins = "gpio27";
|
||||
function = "qup0_l1";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -1184,7 +1184,7 @@
|
||||
qupv3_se5_tx: qupv3_se5_tx {
|
||||
mux {
|
||||
pins = "gpio28";
|
||||
function = "qup0_l2";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
@@ -1197,7 +1197,7 @@
|
||||
qupv3_se5_rx: qupv3_se5_rx {
|
||||
mux {
|
||||
pins = "gpio29";
|
||||
function = "qup0_l3";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
|
||||
@@ -69,7 +69,7 @@
|
||||
<&bimc MASTER_AMPSS_M0 &config_noc SLAVE_QUP_0>,
|
||||
<&system_noc MASTER_QUP_0 &bimc SLAVE_EBI_CH0>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_2uart_tx_active>, <&qupv3_se3_2uart_rx_active>;
|
||||
pinctrl-0 = <&qupv3_se6_2uart_tx_active>, <&qupv3_se6_2uart_rx_active>;
|
||||
pinctrl-1 = <&qupv3_se6_2uart_sleep>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -273,6 +273,14 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
non_secure_display_memory: non_secure_display_region {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
|
||||
size = <0x0 0xa400000>;
|
||||
alignment = <0x0 0x400000>;
|
||||
};
|
||||
|
||||
splash_memory: splash_region@5c000000 {
|
||||
reg = <0x0 0x5c000000 0x0 0x00f00000>;
|
||||
label = "cont_splash_region";
|
||||
@@ -524,6 +532,9 @@
|
||||
reg = <0x61800000 0x2100000>;
|
||||
reg-names = "secapp-region";
|
||||
memory-region = <&qseecom_mem>;
|
||||
qseecom_mem = <&qseecom_mem>;
|
||||
qseecom_ta_mem = <&qseecom_ta_mem>;
|
||||
user_contig_mem = <&user_contig_mem>;
|
||||
qcom,hlos-num-ce-hw-instances = <1>;
|
||||
qcom,hlos-ce-hw-instance = <0>;
|
||||
qcom,qsee-ce-hw-instance = <0>;
|
||||
|
||||
@@ -171,12 +171,6 @@
|
||||
remote-vmids = <0>;
|
||||
};
|
||||
|
||||
mmidgrp800: mmidgrp800 {
|
||||
grp-start-id = <800>;
|
||||
role = "fe";
|
||||
remote-vmids = <0>;
|
||||
};
|
||||
|
||||
mmidgrp900: mmidgrp900 {
|
||||
grp-start-id = <900>;
|
||||
role = "fe";
|
||||
|
||||
258
qcom/sa410m-pcie.dtsi
Normal file
258
qcom/sa410m-pcie.dtsi
Normal file
@@ -0,0 +1,258 @@
|
||||
#include <dt-bindings/clock/qcom,gcc-sa410m.h>
|
||||
|
||||
&soc {
|
||||
pcie0: qcom,pcie@05020000 {
|
||||
compatible = "qcom,pci-msm";
|
||||
cell-index = <0>;
|
||||
|
||||
reg = <0x05020000 0x3000>,
|
||||
<0x05026000 0x1000>,
|
||||
<0x18000000 0xf20>,
|
||||
<0x18000f20 0xa8>,
|
||||
<0x18001000 0x1000>,
|
||||
<0x18100000 0x100000>,
|
||||
<0x05023000 0x1000>;
|
||||
|
||||
reg-names = "parf", "phy", "dm_core", "elbi", "iatu",
|
||||
"conf", "mhi";
|
||||
#adddress-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ranges = <0x01000000 0x0 0x18200000 0x18200000 0x0 0x100000>,
|
||||
<0x02000000 0x0 0x18300000 0x18300000 0x0 0x27d00000>;
|
||||
|
||||
interrupt-parent = <&pcie0>;
|
||||
interrupts = <0 1 2 3 4>;
|
||||
interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
|
||||
"int_d";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0xffffffff>;
|
||||
interrupt-map = <0 0 0 0 &intc GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 1 &intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 2 &intc GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 3 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 4 &intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
qcom,phy-sequence = <0x0800 0x01 0x0
|
||||
0x0804 0x03 0x0
|
||||
0x0034 0x18 0x0
|
||||
0x0038 0x10 0x0
|
||||
0x0070 0x0f 0x0
|
||||
0x00c8 0x01 0x0
|
||||
0x0128 0x00 0x0
|
||||
0x0144 0xff 0x0
|
||||
0x0148 0x1f 0x0
|
||||
0x0194 0x06 0x0
|
||||
0x0048 0x0f 0x0
|
||||
0x0178 0x00 0x0
|
||||
0x019c 0x01 0x0
|
||||
0x018c 0x20 0x0
|
||||
0x0184 0x0a 0x0
|
||||
0x00b4 0x20 0x0
|
||||
0x000c 0x09 0x0
|
||||
0x00ac 0x04 0x0
|
||||
0x00d0 0x82 0x0
|
||||
0x00e4 0x03 0x0
|
||||
0x00e0 0x55 0x0
|
||||
0x00dc 0x55 0x0
|
||||
0x0054 0x00 0x0
|
||||
0x0050 0x0d 0x0
|
||||
0x004c 0x04 0x0
|
||||
0x0174 0x35 0x0
|
||||
0x003c 0x02 0x0
|
||||
0x0040 0x1f 0x0
|
||||
0x0078 0x04 0x0
|
||||
0x0084 0x16 0x0
|
||||
0x0090 0x30 0x0
|
||||
0x010c 0x00 0x0
|
||||
0x0108 0x80 0x0
|
||||
0x00a8 0x01 0x0
|
||||
0x000c 0x0a 0x0
|
||||
0x0010 0x01 0x0
|
||||
0x001c 0x31 0x0
|
||||
0x0020 0x01 0x0
|
||||
0x0014 0x02 0x0
|
||||
0x0018 0x00 0x0
|
||||
0x0024 0x2f 0x0
|
||||
0x0028 0x19 0x0
|
||||
0x0268 0x45 0x0
|
||||
0x0194 0x06 0x0
|
||||
0x024c 0x02 0x0
|
||||
0x02ac 0x12 0x0
|
||||
0x0510 0x1c 0x0
|
||||
0x051c 0x14 0x0
|
||||
0x04d8 0x01 0x0
|
||||
0x04dc 0x00 0x0
|
||||
0x04e0 0xdb 0x0
|
||||
0x0448 0x4b 0x0
|
||||
0x041c 0x04 0x0
|
||||
0x0410 0x04 0x0
|
||||
0x0074 0x19 0x0
|
||||
0x0854 0x04 0x0
|
||||
0x09ac 0x00 0x0
|
||||
0x08a0 0x40 0x0
|
||||
0x09e0 0x00 0x0
|
||||
0x09dc 0x40 0x0
|
||||
0x09a8 0x00 0x0
|
||||
0x08a4 0x40 0x0
|
||||
0x08a8 0x73 0x0
|
||||
0x09b0 0x07 0x0
|
||||
0x09d8 0x99 0x0
|
||||
0x0824 0x15 0x0
|
||||
0x0828 0x0e 0x0
|
||||
0x0800 0x00 0x0
|
||||
0x0808 0x03 0x0>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie0_clkreq_default
|
||||
&pcie0_perst_default
|
||||
&pcie0_wake_default>;
|
||||
|
||||
perst-gpio = <&tlmm 25 0>;
|
||||
wake-gpio = <&tlmm 26 0>;
|
||||
|
||||
gdsc-core-vdd-supply = <&gcc_pcie_0_gdsc>;
|
||||
vreg-1p2-supply = <&L16A>;
|
||||
vreg-0p9-supply = <&L12A>;
|
||||
vreg-cx-supply = <&VDD_CX_LEVEL>;
|
||||
vreg-mx-supply = <&VDD_MX_LEVEL>;
|
||||
|
||||
qcom,vreg-1p2-voltage-level = <1800000 1800000 24000>;
|
||||
qcom,vreg-0p9-voltage-level = <925000 925000 24000>;
|
||||
qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
||||
RPMH_REGULATOR_LEVEL_NOM 0>;
|
||||
qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
|
||||
RPMH_REGULATOR_LEVEL_NOM 0>;
|
||||
|
||||
dma-coherent;
|
||||
qcom,bw-scale = /* Gen1 */
|
||||
<RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
19200000
|
||||
/* Gen2 */
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
RPMH_REGULATOR_LEVEL_LOW_SVS
|
||||
19200000
|
||||
/* Gen3 */
|
||||
RPMH_REGULATOR_LEVEL_NOM
|
||||
RPMH_REGULATOR_LEVEL_NOM
|
||||
100000000>;
|
||||
|
||||
interconnect-names = "icc_path";
|
||||
interconnects = <&sys_noc MASTER_PCIE &bimc_noc SLAVE_EBI_CH0>;
|
||||
|
||||
msi-parent = <&pcie0_msi>;
|
||||
|
||||
qcom,no-l0s-supported;
|
||||
qcom,no-l1-supported;
|
||||
qcom,no-l1ss-supported;
|
||||
qcom,no-aux-clk-sync;
|
||||
|
||||
qcom,max-link-speed = <0x2>;
|
||||
qcom,target-link-speed = <0x2>;
|
||||
|
||||
qcom,ep-latency = <10>;
|
||||
|
||||
qcom,slv-addr-space-size = <0x4000000>;
|
||||
|
||||
qcom,phy-status-offset = <0x974>;
|
||||
qcom,phy-status-bit = <6>;
|
||||
qcom,phy-power-down-offset = <0x804>;
|
||||
qcom,core-preset = <0x77777777>;
|
||||
|
||||
qcom,boot-option = <0x0>;
|
||||
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
qcom,pcie-phy-ver = <2609>;
|
||||
qcom,aux-clk-freq = <20>;
|
||||
|
||||
qcom,smmu-sid-base = <0x0400>;
|
||||
|
||||
iommu-map = <0x0 &apps_smmu 0x0400 0x1>,
|
||||
<0x100 &apps_smmu 0x0401 0x1>,
|
||||
<0x200 &apps_smmu 0x0402 0x1>,
|
||||
<0x300 &apps_smmu 0x0403 0x1>,
|
||||
<0x400 &apps_smmu 0x0404 0x1>,
|
||||
<0x500 &apps_smmu 0x0405 0x1>,
|
||||
<0x600 &apps_smmu 0x0406 0x1>,
|
||||
<0x700 &apps_smmu 0x0407 0x1>,
|
||||
<0x800 &apps_smmu 0x0408 0x1>,
|
||||
<0x900 &apps_smmu 0x0409 0x1>,
|
||||
<0xa00 &apps_smmu 0x040a 0x1>,
|
||||
<0xb00 &apps_smmu 0x040b 0x1>,
|
||||
<0xc00 &apps_smmu 0x040c 0x1>,
|
||||
<0xd00 &apps_smmu 0x040d 0x1>,
|
||||
<0xe00 &apps_smmu 0x040e 0x1>,
|
||||
<0xf00 &apps_smmu 0x040f 0x1>;
|
||||
|
||||
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
|
||||
<&rpmcc RPM_SMD_XO_CLK_SRC>,
|
||||
<&gcc GCC_PCIE_0_AUX_CLK>,
|
||||
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
|
||||
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
|
||||
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
|
||||
<&pcie_0_pipe_clk>;
|
||||
|
||||
clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
|
||||
"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
|
||||
"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
|
||||
"pcie_0_slv_q2a_axi_clk",
|
||||
"pcie_pipe_clk_ext_src";
|
||||
|
||||
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>, <0>, <0>;
|
||||
|
||||
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_0_BCR>,
|
||||
<&gcc GCC_PCIE_0_PHY_BCR>;
|
||||
|
||||
reset-names = "pcie_0_core_reset",
|
||||
"pcie_0_phy_reset";
|
||||
|
||||
pcie0_rp: pcie0_rp {
|
||||
reg = <0 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_msi: qcom,pcie0_msi@0xf200040 {
|
||||
compatible = "qcom,pci-msi";
|
||||
msi-controller;
|
||||
reg = <0xf200040 0x0>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 470 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 471 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 472 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 473 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 474 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 476 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 480 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 481 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 482 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 483 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 484 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 485 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 486 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 487 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 488 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 489 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 490 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 491 IRQ_TYPE_EDGE_RISING>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -739,6 +739,44 @@
|
||||
rclk {
|
||||
pins = "sdc1_rclk";
|
||||
bias-pull-down;
|
||||
pcie0 {
|
||||
pcie0_clkreq_default: pcie0_clkreq_default {
|
||||
mux {
|
||||
pins = "gpio24";
|
||||
function = "PCIE0_CLK_REQ";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio24";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_perst_default: pcie0_perst_default {
|
||||
mux {
|
||||
pins = "gpio25";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio25";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_wake_default: pcie0_wake_default {
|
||||
mux {
|
||||
pins = "gpio26";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio26";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -29,6 +29,7 @@
|
||||
serial0 = &qupv3_se4_2uart;
|
||||
qpic_nand1 = &qnand_1;
|
||||
mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
|
||||
pci-domain0 = &pcie0;
|
||||
};
|
||||
|
||||
firmware: firmware {};
|
||||
@@ -203,7 +204,7 @@
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7";
|
||||
bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 pcie_ports=compat";
|
||||
};
|
||||
|
||||
soc: soc { };
|
||||
@@ -766,7 +767,7 @@
|
||||
/* Voting for max b/w on PNOC bus for now */
|
||||
<1057800 725760>;
|
||||
|
||||
iommus = <&apps_smmu 0x100 0x7>;
|
||||
iommus = <&apps_smmu 0x100 0x3>;
|
||||
qcom,iommu-dma = "bypass";
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -936,6 +937,7 @@
|
||||
#include "monaco-gdsc.dtsi"
|
||||
#include "sa410m-qupv3.dtsi"
|
||||
#include "sa410m-dma-heap.dtsi"
|
||||
#include "sa410m-pcie.dtsi"
|
||||
|
||||
&gcc_emac0_gdsc {
|
||||
status = "ok";
|
||||
|
||||
@@ -78,6 +78,9 @@
|
||||
qcom,vddp-ref-clk-supply = <&pm8150_2_l5>;
|
||||
qcom,vddp-ref-clk-max-microamp = <100>;
|
||||
|
||||
/* Disable Write Booster Feature */
|
||||
qcom,disable-wb-support;
|
||||
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
|
||||
@@ -19,3 +19,23 @@
|
||||
|
||||
&soc {
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb2_phy0 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&usb_qmp_phy {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
309
qcom/sa8155-vm-usb.dtsi
Normal file
309
qcom/sa8155-vm-usb.dtsi
Normal file
@@ -0,0 +1,309 @@
|
||||
#include <dt-bindings/phy/qcom,sm8150-qmp-usb3.h>
|
||||
|
||||
&soc {
|
||||
/* Primary USB port related controller */
|
||||
usb0: ssusb@a600000 {
|
||||
compatible = "qcom,dwc-usb3-msm";
|
||||
reg = <0xa600000 0x100000>;
|
||||
reg-names = "core_base";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 9 IRQ_TYPE_EDGE_RISING>,
|
||||
<&pdc 8 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "pwr_event_irq","dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq";
|
||||
qcom,use-pdc-interrupts;
|
||||
|
||||
USB3_GDSC-supply = <&usb30_prim_gdsc>;
|
||||
clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
|
||||
<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
|
||||
|
||||
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
||||
"utmi_clk", "sleep_clk";
|
||||
|
||||
resets = <&gcc GCC_USB30_PRIM_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qcom,core-clk-rate = <200000000>;
|
||||
qcom,core-clk-rate-hs = <66666667>;
|
||||
qcom,ignore-wakeup-src-in-hostmode;
|
||||
|
||||
status = "disabled";
|
||||
dwc3@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0xa600000 0xcd00>;
|
||||
iommus = <&apps_smmu 0x140 0x0>;
|
||||
qcom,iommu-dma = "bypass";
|
||||
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
|
||||
snps,disable-clk-gating;
|
||||
snps,has-lpm-erratum;
|
||||
snps,hird-threshold = /bits/ 8 <0x0>;
|
||||
snps,is-utmi-l1-suspend;
|
||||
snps,usb2-gadget-lpm-disable;
|
||||
tx-fifo-resize;
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
usb-role-switch;
|
||||
};
|
||||
};
|
||||
|
||||
/* Primary USB port related High Speed PHY */
|
||||
usb2_phy0: hsphy@88e2000 {
|
||||
compatible = "qcom,usb-hsphy-snps-femto";
|
||||
reg = <0x88e2000 0x110>,
|
||||
<0x007801f8 0x4>;
|
||||
reg-names = "hsusb_phy_base",
|
||||
"phy_rcal_reg";
|
||||
|
||||
vdd-supply = <&L5A>;
|
||||
vdda18-supply = <&L12A>;
|
||||
vdda33-supply = <&L2A>;
|
||||
qcom,vdd-voltage-level = <0 880000 880000>;
|
||||
|
||||
clocks = <&dummycc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
|
||||
clock-names = "ref_clk_src", "ref_clk";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
|
||||
reset-names = "phy_reset";
|
||||
qcom,param-override-seq = <0x43 0x70>;
|
||||
qcom,rcal-mask = <0x1e00000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_nop_phy: usb_nop_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
};
|
||||
|
||||
/* Secondary USB port related controller */
|
||||
usb1: ssusb@a800000 {
|
||||
compatible = "qcom,dwc-usb3-msm";
|
||||
reg = <0x0a800000 0x100000>;
|
||||
reg-names = "core_base";
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 11 IRQ_TYPE_EDGE_RISING>,
|
||||
<&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&pdc 10 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "pwr_event_irq","dp_hs_phy_irq",
|
||||
"ss_phy_irq","dm_hs_phy_irq";
|
||||
qcom,use-pdc-interrupts;
|
||||
qcom,default-mode-host;
|
||||
qcom,ignore-wakeup-src-in-hostmode;
|
||||
|
||||
USB3_GDSC-supply = <&usb30_sec_gdsc>;
|
||||
clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
|
||||
<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
|
||||
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
||||
<&gcc GCC_USB30_SEC_SLEEP_CLK>;
|
||||
|
||||
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
||||
"utmi_clk", "sleep_clk";
|
||||
|
||||
resets = <&gcc GCC_USB30_SEC_BCR>;
|
||||
reset-names = "core_reset";
|
||||
|
||||
qcom,core-clk-rate = <200000000>;
|
||||
qcom,core-clk-rate-hs = <66666667>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
dwc3@a800000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0a800000 0xd941>;
|
||||
iommus = <&apps_smmu 0x160 0x0>;
|
||||
qcom,iommu-dma = "bypass";
|
||||
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
usb-phy = <&usb2_phy1>, <&usb_qmp_phy>;
|
||||
snps,disable-clk-gating;
|
||||
snps,has-lpm-erratum;
|
||||
snps,hird-threshold = /bits/ 8 <0x0>;
|
||||
snps,ssp-u3-u0-quirk;
|
||||
snps,is-utmi-l1-suspend;
|
||||
snps,usb2-gadget-lpm-disable;
|
||||
snps,dis-u1-entry-quirk;
|
||||
snps,dis-u2-entry-quirk;
|
||||
snps,force-gen1;
|
||||
tx-fifo-resize;
|
||||
maximum-speed = "super-speed";
|
||||
dr_mode = "otg";
|
||||
usb-role-switch;
|
||||
};
|
||||
};
|
||||
|
||||
/* Secondary USB port related High Speed PHY */
|
||||
usb2_phy1: hsphy@88e3000 {
|
||||
compatible = "qcom,usb-hsphy-snps-femto";
|
||||
reg = <0x88e3000 0x110>,
|
||||
<0x007801f8 0x4>;
|
||||
reg-names = "hsusb_phy_base",
|
||||
"phy_rcal_reg";
|
||||
|
||||
vdd-supply = <&L5A>;
|
||||
vdda18-supply = <&L12A>;
|
||||
vdda33-supply = <&L2A>;
|
||||
qcom,vdd-voltage-level = <0 880000 880000>;
|
||||
|
||||
clocks = <&dummycc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_CLK>;
|
||||
clock-names = "ref_clk_src", "ref_clk";
|
||||
|
||||
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
|
||||
reset-names = "phy_reset";
|
||||
qcom,param-override-seq = <0x43 0x70
|
||||
0x01 0xb0>;
|
||||
qcom,rcal-mask = <0x1e00000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Secondary USB port related QMP PHY */
|
||||
usb_qmp_phy: ssphy@88eb000 {
|
||||
compatible = "qcom,usb-ssphy-qmp-v2";
|
||||
reg = <0x88eb000 0x1000>,
|
||||
<0x088eb88c 0x4>;
|
||||
reg-names = "qmp_phy_base",
|
||||
"pcs_clamp_enable_reg";
|
||||
|
||||
vdd-supply = <&L5A>;
|
||||
qcom,vdd-voltage-level = <0 880000 880000>;
|
||||
qcom,vdd-max-load-uA = <47000>;
|
||||
core-supply = <&L8C>;
|
||||
qcom,qmp-phy-init-seq =
|
||||
/* <reg_offset, value, delay> */
|
||||
<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a 0
|
||||
USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
|
||||
USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0
|
||||
USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0
|
||||
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0
|
||||
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0
|
||||
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
|
||||
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0
|
||||
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0
|
||||
USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x02 0
|
||||
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
|
||||
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
|
||||
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
|
||||
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
|
||||
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
|
||||
USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0
|
||||
USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0
|
||||
USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
|
||||
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
|
||||
USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
|
||||
USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0
|
||||
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0
|
||||
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0
|
||||
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
|
||||
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
|
||||
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
|
||||
USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0
|
||||
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
|
||||
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
|
||||
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0
|
||||
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0
|
||||
USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0
|
||||
USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0
|
||||
USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
|
||||
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0
|
||||
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
|
||||
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0
|
||||
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
|
||||
USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
|
||||
USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xa4 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0x7f 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0x37 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x2f 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xaf 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb6 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x0b 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0
|
||||
USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0X99 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0a 0
|
||||
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
|
||||
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x00 0
|
||||
USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0
|
||||
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
|
||||
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0
|
||||
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0
|
||||
USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04 0
|
||||
USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
|
||||
USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
|
||||
USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0
|
||||
USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0
|
||||
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0
|
||||
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0
|
||||
USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x20 0
|
||||
USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0
|
||||
USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0
|
||||
USB3_UNI_QSERDES_TX_LANE_MODE_1 0x95 0
|
||||
USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0
|
||||
USB3_UNI_QSERDES_TX_RES_CODE_LANE_TX 0xe4 0
|
||||
USB3_UNI_QSERDES_TX_RES_CODE_LANE_RX 0xd0 0
|
||||
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0
|
||||
USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0
|
||||
USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0
|
||||
USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0
|
||||
USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0
|
||||
USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0
|
||||
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0
|
||||
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
|
||||
USB3_UNI_PCS_RX_SIGDET_LVL 0xaa 0
|
||||
USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
|
||||
USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0
|
||||
USB3_UNI_PCS_CDR_RESET_TIME 0x0a 0
|
||||
USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0
|
||||
USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0
|
||||
USB3_UNI_PCS_EQ_CONFIG1 0x4b 0
|
||||
USB3_UNI_PCS_EQ_CONFIG5 0x10 0
|
||||
USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0
|
||||
USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0
|
||||
0xffffffff 0xffffffff 0x00>;
|
||||
|
||||
qcom,qmp-phy-reg-offset =
|
||||
<USB3_UNI_PCS_PCS_STATUS1
|
||||
USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
|
||||
USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
|
||||
USB3_UNI_PCS_POWER_DOWN_CONTROL
|
||||
USB3_UNI_PCS_SW_RESET
|
||||
USB3_UNI_PCS_START_CONTROL>;
|
||||
|
||||
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
|
||||
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
|
||||
<&dummycc RPMH_CXO_CLK>,
|
||||
<&gcc GCC_USB3_SEC_CLKREF_CLK>,
|
||||
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
|
||||
clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
|
||||
"ref_clk", "com_aux_clk";
|
||||
|
||||
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
|
||||
<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
|
||||
reset-names = "phy_reset", "phy_phy_reset";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
@@ -182,6 +182,8 @@
|
||||
#iommu-cells = <2>;
|
||||
qcom,skip-init;
|
||||
qcom,use-3-lvl-tables;
|
||||
qcom,handoff-smrs = <0xffff 0x0>;
|
||||
qcom,multi-match-handoff-smr;
|
||||
qcom,disable-atos;
|
||||
#global-interrupts = <1>;
|
||||
#size-cells = <1>;
|
||||
@@ -296,6 +298,7 @@
|
||||
#include "sm8150-pinctrl.dtsi"
|
||||
#include "sa8155-vm-pcie.dtsi"
|
||||
#include "sa8155-vm-qupv3.dtsi"
|
||||
#include "sa8155-vm-usb.dtsi"
|
||||
|
||||
&tlmm {
|
||||
/delete-property/ wakeup-parent;
|
||||
@@ -411,3 +414,64 @@
|
||||
&qupv3_se12_2uart {
|
||||
status = "disabled";
|
||||
};
|
||||
&soc {
|
||||
tcsr_compute_signal_glb: syscon@0x1fd8000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x1fd8000 0x1000>;
|
||||
};
|
||||
|
||||
tcsr_compute_signal_sender0: syscon@0x1fd9000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x1fd9000 0x1000>;
|
||||
};
|
||||
|
||||
tcsr_compute_signal_sender1: syscon@0x1fdd000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x1fdd000 0x1000>;
|
||||
};
|
||||
|
||||
tcsr_compute_signal_receiver0: syscon@0x1fdb000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x1fdb000 0x1000>;
|
||||
};
|
||||
|
||||
tcsr_compute_signal_receiver1: syscon@0x1fdf000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x1fdf000 0x1000>;
|
||||
};
|
||||
|
||||
hgsl_tcsr_sender0: hgsl_tcsr_sender0 {
|
||||
compatible = "qcom,hgsl-tcsr-sender";
|
||||
syscon = <&tcsr_compute_signal_sender0>;
|
||||
syscon-glb = <&tcsr_compute_signal_glb>;
|
||||
};
|
||||
|
||||
hgsl_tcsr_sender1: hgsl_tcsr_sender1 {
|
||||
compatible = "qcom,hgsl-tcsr-sender";
|
||||
syscon = <&tcsr_compute_signal_sender1>;
|
||||
syscon-glb = <&tcsr_compute_signal_glb>;
|
||||
};
|
||||
|
||||
hgsl_tcsr_receiver0: hgsl_tcsr_receiver0 {
|
||||
compatible = "qcom,hgsl-tcsr-receiver";
|
||||
syscon = <&tcsr_compute_signal_receiver0>;
|
||||
interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
hgsl_tcsr_receiver1: hgsl_tcsr_receiver1 {
|
||||
compatible = "qcom,hgsl-tcsr-receiver";
|
||||
syscon = <&tcsr_compute_signal_receiver1>;
|
||||
interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
msm_gpu_hyp: qcom,hgsl@0x2c00000 {
|
||||
compatible = "qcom,hgsl";
|
||||
reg = <0x2c00000 0x8>, <0x2c8f000 0x4>;
|
||||
reg-names = "hgsl_reg_hwinf", "hgsl_reg_gmucx";
|
||||
|
||||
qcom,glb-db-senders = <&hgsl_tcsr_sender0
|
||||
&hgsl_tcsr_sender1>;
|
||||
qcom,glb-db-receivers = <&hgsl_tcsr_receiver0
|
||||
&hgsl_tcsr_receiver1>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -6,6 +6,9 @@
|
||||
model = "Qualcomm Technologies, Inc. SA8195P";
|
||||
qcom,msm-name = "SA8195P";
|
||||
qcom,msm-id = <405 0x20000>;
|
||||
aliases {
|
||||
hsuart0 = &qupv3_se17_4uart;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
@@ -57,5 +60,33 @@
|
||||
qcom,vccq-parent-supply = <&pm8195_1_s2>;
|
||||
qcom,vccq-parent-max-microamp = <210000>;
|
||||
|
||||
/* Disable Write Booster Feature */
|
||||
qcom,disable-wb-support;
|
||||
|
||||
status= "ok";
|
||||
};
|
||||
|
||||
/* Add CNSS power ctrl nodes specific to SA8195 */
|
||||
&soc {
|
||||
/* PWR_CTR2_VDD_1P8 supply */
|
||||
vreg_conn_1p8: vreg_conn_1p8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vreg_conn_1p8";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&conn_power_1p8_active>;
|
||||
startup-delay-us = <4000>;
|
||||
enable-active-high;
|
||||
gpio = <&tlmm 173 0>;
|
||||
};
|
||||
|
||||
/* PWR_CTR1_VDD_PA supply */
|
||||
vreg_conn_pa: vreg_conn_pa {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vreg_conn_pa";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&conn_power_pa_active>;
|
||||
startup-delay-us = <4000>;
|
||||
enable-active-high;
|
||||
gpio = <&tlmm 174 0>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -31,8 +31,8 @@
|
||||
qcom,ap2mdm-soft-reset-gpio = <&pm8550_gpios 1 0>;
|
||||
|
||||
reg-names = "l10b";
|
||||
l10c-supply = <&L10B>;
|
||||
l10c-uV-uA = <1200000 100000>;
|
||||
l10b-supply = <&L10B>;
|
||||
l10b-uV-uA = <1200000 100000>;
|
||||
|
||||
qcom,esoc-skip-restart-for-mdm-crash;
|
||||
status = "ok";
|
||||
|
||||
@@ -55,3 +55,11 @@
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
};
|
||||
|
||||
&debugcc {
|
||||
clocks = <&bi_tcxo>, <&gcc 0>;
|
||||
};
|
||||
|
||||
&cpufreq_hw {
|
||||
clocks = <&bi_tcxo>, <&gcc GPLL0>;
|
||||
};
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
|
||||
/ {
|
||||
VDD_MODEM_LEVEL:
|
||||
VDD_CX_LEVEL:
|
||||
S1A_LEVEL:
|
||||
pmx35_s1_level: regulator-pmx35-s1-level {
|
||||
|
||||
@@ -20,7 +20,7 @@
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "pcie_ports=compat";
|
||||
bootargs = "pcie_ports=compat cpufreq.default_governor=performance";
|
||||
};
|
||||
|
||||
memory { device_type = "memory"; reg = <0 0>; };
|
||||
@@ -141,6 +141,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0x0>;
|
||||
qcom,freq-domain = <&cpufreq_hw 0>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -441,6 +442,44 @@
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
apsscc: syscon@17011000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x17011000 0x20>;
|
||||
};
|
||||
|
||||
mccc: syscon@190ba000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x190ba000 0x54>;
|
||||
};
|
||||
|
||||
debugcc: clock-controller@0 {
|
||||
compatible = "qcom,sdxbaagha-debugcc";
|
||||
qcom,gcc = <&gcc>;
|
||||
qcom,mccc = <&mccc>;
|
||||
qcom,apsscc = <&apsscc>;
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
||||
<&gcc 0>;
|
||||
clock-names = "xo_clk_src",
|
||||
"gcc";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
cpufreq_hw: qcom,cpufreq-hw {
|
||||
compatible = "qcom,cpufreq-epss";
|
||||
reg = <0x17191000 0x1000>;
|
||||
reg-names = "freq-domain0";
|
||||
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
||||
clock-names = "xo", "alternate";
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "dcvsh0_int";
|
||||
#freq-domain-cells = <1>;
|
||||
};
|
||||
|
||||
qcom,cpufreq-hw-debug {
|
||||
compatible = "qcom,cpufreq-hw-epss-debug";
|
||||
qcom,freq-hw-domain = <&cpufreq_hw 0>;
|
||||
};
|
||||
|
||||
/* GCC GDSCs */
|
||||
gcc_emac0_gdsc: qcom,gdsc@f1004 {
|
||||
compatible = "qcom,gdsc";
|
||||
|
||||
@@ -31,8 +31,8 @@
|
||||
qcom,ap2mdm-soft-reset-gpio = <&pm8550_gpios 1 0>;
|
||||
|
||||
reg-names = "l10b";
|
||||
l10c-supply = <&L10B>;
|
||||
l10c-uV-uA = <1200000 100000>;
|
||||
l10b-supply = <&L10B>;
|
||||
l10b-uV-uA = <1200000 100000>;
|
||||
|
||||
qcom,esoc-skip-restart-for-mdm-crash;
|
||||
status = "ok";
|
||||
|
||||
@@ -31,7 +31,7 @@
|
||||
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,gpii-mask = <0xfff>;
|
||||
qcom,gpii-mask = <0x7f>;
|
||||
qcom,ev-factor = <2>;
|
||||
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
|
||||
qcom,gpi-ee-offset = <0x10000>;
|
||||
@@ -168,6 +168,7 @@
|
||||
dmas = <&gpi_dma0 0 2 3 64 0>,
|
||||
<&gpi_dma0 1 2 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,shared;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
Reference in New Issue
Block a user