ARM: dts: msm: set ddr bus-width to 8

Set DDR bus-width to 8 for khaje.

Change-Id: If407376ada9f69e26ece314621fdbdad74e01c32
This commit is contained in:
Swetha Chikkaboraiah
2022-09-29 16:02:05 +05:30
committed by Gerrit - the friendly Code Review server
parent aab1234117
commit 8de7322c63

View File

@@ -3502,7 +3502,7 @@
qcom_ddr_dcvs_hw: ddr {
compatible = "qcom,dcvs-hw";
qcom,dcvs-hw-type = <0>;
qcom,bus-width = <4>;
qcom,bus-width = <8>;
qcom,freq-tbl = <&ddr_freq_table>;
ddr_dcvs_sp: sp {