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https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
ARM: dts: msm: Add HS USB PHY support in Cinder
Add HS USB Phy node in cinder usb for supporting HS mode. some voltage regualtors are different for RU & DU, hence the voltage regulators are added in corresponding target DT files. Change-Id: I3237ef28f99bf9f01495363f19013da1af3c8013
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@@ -148,3 +148,11 @@
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reg = <0x0 0xc3200000 0x0 0x12c00000>;
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};
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};
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&soc {
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usb2_phy0 {
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vdd-supply = <&L8A>;
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vdda18-supply = <&L14A>;
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vdda33-supply = <&L2A>;
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qcom,vdd-voltage-level = <0 888000 920000>;
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};
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};
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@@ -143,3 +143,11 @@
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reg = <0x0 0xb4e00000 0x0 0x3200000>;
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};
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};
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&soc {
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usb2_phy0 {
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vdd-supply = <&L5A>;
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vdda18-supply = <&L14A>;
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vdda33-supply = <&L2A>;
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qcom,vdd-voltage-level = <0 880000 920000>;
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};
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};
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@@ -28,10 +28,6 @@
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qcom,tcsr-not-supported;
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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usb_emu_phy: phy@a784000 {
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compatible = "qcom,usb-emu-phy";
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reg = <0x0a784000 0x9500>;
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@@ -48,6 +48,7 @@
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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dma-coherent;
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usb-phy = <&usb2_phy0>, <&usb_nop_phy>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x0>;
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@@ -60,4 +61,24 @@
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maximum-speed = "super-speed-plus";
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};
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};
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/* USB port related High Speed PHY */
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usb2_phy0: hsphy@88e3000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0x88e3000 0x120>,
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<0x088e2000 0x4>;
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reg-names = "hsusb_phy_base",
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"eud_enable_reg";
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB2_CLKREF_EN>;
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clock-names = "ref_clk_src", "ref_clk";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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};
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usb_nop_phy: usb_nop_phy {
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compatible = "usb-nop-xceiv";
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};
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};
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