mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
ARM: dts: msm: Add PCIe configuration for sdxpinn
These changes enables PCIe controller and add related configuration for sdxpinn target. Change-Id: I5261730a6793ab8f7caf0cc84c86ff1741d412a1
This commit is contained in:
Jyothi Kumar Seerapu
414
qcom/sdxpinn-pcie.dtsi
Normal file
414
qcom/sdxpinn-pcie.dtsi
Normal file
@@ -0,0 +1,414 @@
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#include <dt-bindings/clock/qcom,gcc-sdxpinn.h>
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&soc {
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pcie0: qcom,pcie@1bf0000 {
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compatible = "qcom,pci-msm";
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reg = <0x01bf0000 0x4000>,
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<0x01bf7000 0x2000>,
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<0x48000000 0xf20>,
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<0x48000f20 0xa8>,
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<0x48001000 0x2000>,
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<0x48100000 0x100000>,
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<0x01bf4000 0x1000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu",
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"conf", "mhi";
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cell-index = <0>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x48200000 0x48200000 0x0 0x100000>,
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<0x02000000 0x0 0x48300000 0x48300000 0x0 0x3d00000>;
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interrupt-parent = <&pcie0>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie0_msi>;
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perst-gpio = <&tlmm 44 0>;
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wake-gpio = <&tlmm 42 0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie0_clkreq_default
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&pcie0_perst_default
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&pcie0_wake_default>;
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pinctrl-1 = <&pcie0_clkreq_sleep
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&pcie0_perst_default
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&pcie0_wake_default>;
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gdsc-core-vdd-supply = <&gcc_pcie_gdsc>;
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gdsc-phy-vdd-supply = <&gcc_pcie_phy_gdsc>;
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vreg-1p2-supply = <&pmx75_l1>;
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vreg-0p9-supply = <&pmx75_l4>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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vreg-mx-supply = <&VDD_MXA_LEVEL>;
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qcom,vreg-1p2-voltage-level = <1200000 1200000 21700>;
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qcom,vreg-0p9-voltage-level = <880000 880000 177000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000
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/* Gen4 */
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RPMH_REGULATOR_LEVEL_NOM
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RPMH_REGULATOR_LEVEL_NOM
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100000000>;
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//interconnect-names = "icc_path";
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//interconnects = <&system_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;
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clocks = <&gcc GCC_PCIE_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_AUX_CLK>,
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<&gcc GCC_PCIE_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_CLKREF_EN>,
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<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_SLEEP_CLK>,
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<&gcc GCC_PCIE_RCHNG_PHY_CLK>,
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<&gcc GCC_PCIE_PIPE_CLK_SRC>,
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<&pcie_pipe_clk>;
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clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
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"pcie_aux_clk", "pcie_cfg_ahb_clk",
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"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
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"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
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"pcie_sleep_clk", "pcie_phy_refgen_clk",
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"pcie_pipe_clk_mux", "pcie_pipe_clk_ext_src";
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clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <0>, <100000000>, <0>, <0>;
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clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
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<0>, <0>, <0>, <0>;
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resets = <&gcc GCC_PCIE_BCR>,
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<&gcc GCC_PCIE_PHY_BCR>;
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reset-names = "pcie_core_reset",
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"pcie_phy_reset";
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//qcom,smmu-sid-base = <0x0800>;
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//iommu-map = <0x0 &apps_smmu 0x0800 0x1>,
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// <0x100 &apps_smmu 0x0801 0x1>;
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qcom,aux-clk-freq = <20>; /* 19.2 MHz */
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qcom,tpwr-on-scale = <1>;
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qcom,tpwr-on-value = <9>;
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qcom,eq-fmdc-t-min-phase23 = <1>;
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qcom,slv-addr-space-size = <0x4000000>;
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qcom,ep-latency = <10>;
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qcom,num-parf-testbus-sel = <0xb9>;
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pcie0_rp: pcie0_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie0_msi: qcom,pcie0_msi@a0000000 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0xa0000000 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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qcom,snps;
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};
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pcie1: qcom,pcie@1c08000 {
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compatible = "qcom,pci-msm";
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reg = <0x01c08000 0x4000>,
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<0x01c0e000 0x2000>,
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<0x68000000 0xf1d>,
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<0x68000f20 0xa8>,
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<0x68001000 0x1000>,
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<0x68100000 0x100000>,
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<0x01c0c000 0x1000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu",
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"conf", "mhi";
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cell-index = <1>;
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x68200000 0x68200000 0x0 0x100000>,
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<0x02000000 0x0 0x68300000 0x68300000 0x0 0x3d00000>;
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interrupt-parent = <&pcie1>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie1_msi>;
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perst-gpio = <&tlmm 125 0>;
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wake-gpio = <&tlmm 123 0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie1_clkreq_default
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&pcie1_perst_default
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&pcie1_wake_default>;
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pinctrl-1 = <&pcie1_clkreq_sleep
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&pcie1_perst_default
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&pcie1_wake_default>;
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gdsc-core-vdd-supply = <&gcc_pcie_1_gdsc>;
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gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>;
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vreg-1p2-supply = <&pmx75_l1>;
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vreg-0p9-supply = <&pmx75_l4>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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vreg-mx-supply = <&VDD_MXA_LEVEL>;
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qcom,vreg-1p2-voltage-level = <1200000 1200000 12000>;
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qcom,vreg-0p9-voltage-level = <912000 880000 77800>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000>;
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//interconnect-names = "icc_path";
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//interconnects = <&system_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>;
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clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_1_AUX_CLK>,
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<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_1_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_1_CLKREF_EN>,
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<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
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<&pcie_1_pipe_clk>;
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clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
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"pcie_aux_clk", "pcie_cfg_ahb_clk",
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"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
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"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
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"pcie_phy_refgen_clk", "pcie_pipe_clk_mux",
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"pcie_pipe_clk_ext_src";
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clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
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<0>, <0>, <100000000>, <0>, <0>;
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clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
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<0>, <0>, <0>;
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resets = <&gcc GCC_PCIE_1_BCR>,
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<&gcc GCC_PCIE_1_PHY_BCR>;
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reset-names = "pcie_1_core_reset",
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"pcie_1_phy_reset";
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//qcom,smmu-sid-base = <0x0880>;
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//iommu-map = <0x0 &apps_smmu 0x0880 0x1>,
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// <0x100 &apps_smmu 0x0881 0x1>;
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qcom,aux-clk-freq = <20>; /* 19.2 MHz */
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qcom,tpwr-on-scale = <1>;
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qcom,tpwr-on-value = <9>;
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qcom,eq-fmdc-t-min-phase23 = <1>;
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qcom,slv-addr-space-size = <0x4000000>;
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qcom,ep-latency = <10>;
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qcom,num-parf-testbus-sel = <0xb9>;
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pcie1_rp: pcie1_rp {
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reg = <0 0 0 0 0>;
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};
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};
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pcie1_msi: qcom,pcie1_msi@a0000000 {
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compatible = "qcom,pci-msi";
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msi-controller;
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reg = <0xa0000000 0x0>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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qcom,snps;
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};
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pcie2: qcom,pcie@1c10000 {
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compatible = "qcom,pci-msm";
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reg = <0x01c10000 0x4000>,
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<0x1c16000 0x2000>,
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<0x6c000000 0xf1d>,
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<0x6c000f20 0xa8>,
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<0x6c001000 0x1000>,
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<0x6c100000 0x100000>,
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<0x01c14000 0x1000>;
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reg-names = "parf", "phy", "dm_core", "elbi", "iatu",
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"conf", "mhi";
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cell-index = <2>;
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linux,pci-domain = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x6c200000 0x6c200000 0x0 0x100000>,
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<0x02000000 0x0 0x6c300000 0x6c300000 0x0 0x3d00000>;
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interrupt-parent = <&pcie2>;
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interrupts = <0 1 2 3 4>;
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interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
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"int_d";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0xffffffff>;
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interrupt-map = <0 0 0 0 &intc GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH
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0 0 0 1 &intc GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH
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0 0 0 2 &intc GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH
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0 0 0 3 &intc GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH
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0 0 0 4 &intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
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msi-parent = <&pcie2_msi>;
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perst-gpio = <&tlmm 122 0>;
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wake-gpio = <&tlmm 120 0>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pcie2_clkreq_default
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&pcie2_perst_default
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&pcie2_wake_default>;
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pinctrl-1 = <&pcie2_clkreq_sleep
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&pcie2_perst_default
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&pcie2_wake_default>;
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gdsc-core-vdd-supply = <&gcc_pcie_2_gdsc>;
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gdsc-phy-vdd-supply = <&gcc_pcie_2_phy_gdsc>;
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vreg-1p2-supply = <&pmx75_l1>;
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vreg-0p9-supply = <&pmx75_l4>;
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vreg-cx-supply = <&VDD_CX_LEVEL>;
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vreg-mx-supply = <&VDD_MXA_LEVEL>;
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qcom,vreg-1p2-voltage-level = <1200000 1200000 15000>;
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qcom,vreg-0p9-voltage-level = <912000 880000 48000>;
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qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
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RPMH_REGULATOR_LEVEL_NOM 0>;
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qcom,bw-scale = /* Gen1 */
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<RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000
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/* Gen2 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000
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/* Gen3 */
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RPMH_REGULATOR_LEVEL_LOW_SVS
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RPMH_REGULATOR_LEVEL_LOW_SVS
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100000000>;
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//interconnect-names = "icc_path";
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//interconnects = <&system_noc MASTER_PCIE_2 &mc_virt SLAVE_EBI1>;
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clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_PCIE_2_AUX_CLK>,
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<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_2_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_2_CLKREF_EN>,
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<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
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<&gcc GCC_PCIE_2_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_2_PIPE_CLK_SRC>,
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<&pcie_2_pipe_clk>;
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clock-names = "pcie_pipe_clk", "pcie_ref_clk_src",
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"pcie_aux_clk", "pcie_cfg_ahb_clk",
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"pcie_mstr_axi_clk", "pcie_slv_axi_clk",
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"pcie_clkref_en", "pcie_slv_q2a_axi_clk",
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"pcie_phy_refgen_clk","pcie_pipe_clk_mux",
|
||||
"pcie_pipe_clk_ext_src";
|
||||
clock-frequency = <0>, <0>, <19200000>, <0>, <0>, <0>,
|
||||
<0>, <0>, <100000000>, <0>, <0>;
|
||||
clock-suppressible = <0>, <0>, <0>, <0>, <0>, <0>, <1>, <0>,
|
||||
<0>, <0>, <0>;
|
||||
|
||||
resets = <&gcc GCC_PCIE_2_BCR>,
|
||||
<&gcc GCC_PCIE_2_PHY_BCR>;
|
||||
reset-names = "pcie_2_core_reset",
|
||||
"pcie_2_phy_reset";
|
||||
|
||||
//qcom,smmu-sid-base = <0x0900>;
|
||||
//iommu-map = <0x0 &apps_smmu 0x0900 0x1>,
|
||||
// <0x100 &apps_smmu 0x0901 0x1>;
|
||||
|
||||
qcom,aux-clk-freq = <20>; /* 19.2 MHz */
|
||||
qcom,tpwr-on-scale = <1>;
|
||||
qcom,tpwr-on-value = <9>;
|
||||
qcom,eq-fmdc-t-min-phase23 = <1>;
|
||||
qcom,slv-addr-space-size = <0x4000000>;
|
||||
qcom,ep-latency = <10>;
|
||||
qcom,num-parf-testbus-sel = <0xb9>;
|
||||
|
||||
pcie2_rp: pcie2_rp {
|
||||
reg = <0 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_msi: qcom,pcie2_msi@a0000000 {
|
||||
compatible = "qcom,pci-msi";
|
||||
msi-controller;
|
||||
reg = <0xa0000000 0x0>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,snps;
|
||||
};
|
||||
};
|
||||
@@ -39,4 +39,166 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie0 {
|
||||
pcie0_perst_default: pcie0_perst_default {
|
||||
mux {
|
||||
pins = "gpio44";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio44";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_clkreq_default: pcie0_clkreq_default {
|
||||
mux {
|
||||
pins = "gpio43";
|
||||
function = "pcie0_clkreqn";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio43";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_wake_default: pcie0_wake_default {
|
||||
mux {
|
||||
pins = "gpio42";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio42";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_clkreq_sleep: pcie0_clkreq_sleep {
|
||||
mux {
|
||||
pins = "gpio43";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio43";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie1 {
|
||||
pcie1_perst_default: pcie1_perst_default {
|
||||
mux {
|
||||
pins = "gpio125";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio125";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_clkreq_default: pcie1_clkreq_default {
|
||||
mux {
|
||||
pins = "gpio124";
|
||||
function = "pcie1_clkreqn";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio124";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_wake_default: pcie1_wake_default {
|
||||
mux {
|
||||
pins = "gpio123";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio123";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_clkreq_sleep: pcie1_clkreq_sleep {
|
||||
mux {
|
||||
pins = "gpio124";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio124";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie2 {
|
||||
pcie2_perst_default: pcie2_perst_default {
|
||||
mux {
|
||||
pins = "gpio122";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio122";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_clkreq_default: pcie2_clkreq_default {
|
||||
mux {
|
||||
pins = "gpio121";
|
||||
function = "pcie2_clkreqn";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio121";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_wake_default: pcie2_wake_default {
|
||||
mux {
|
||||
pins = "gpio120";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio120";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie2_clkreq_sleep: pcie2_clkreq_sleep {
|
||||
mux {
|
||||
pins = "gpio121";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio121";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -6,6 +6,64 @@
|
||||
clock-frequency = <500000>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
pcie0: qcom,pcie@1bf0000 {
|
||||
status = "disabled";
|
||||
reg = <0x01bf0000 0x4000>,
|
||||
<0x01bf7000 0x2000>,
|
||||
<0x48000000 0xf20>,
|
||||
<0x48000f20 0xa8>,
|
||||
<0x48001000 0x2000>,
|
||||
<0x48100000 0x100000>,
|
||||
<0x01bf4000 0x1000>,
|
||||
<0x01bf7500 0x1000>;
|
||||
reg-names = "parf", "phy", "dm_core", "elbi", "iatu",
|
||||
"conf", "mhi", "rumi";
|
||||
qcom,target-link-speed = <0x1>;
|
||||
qcom,link-check-max-count = <200>; /* 1 sec */
|
||||
qcom,no-l1-supported;
|
||||
qcom,no-l1ss-supported;
|
||||
qcom,no-aux-clk-sync;
|
||||
};
|
||||
|
||||
pcie1: qcom,pcie@1c08000 {
|
||||
status = "disabled";
|
||||
reg = <0x01c08000 0x4000>,
|
||||
<0x01c0e000 0x2000>,
|
||||
<0x68000000 0xf1d>,
|
||||
<0x68000f20 0xa8>,
|
||||
<0x68001000 0x1000>,
|
||||
<0x68100000 0x100000>,
|
||||
<0x01c0c000 0x1000>,
|
||||
<0x01c0d000 0x1000>;
|
||||
reg-names = "parf", "phy", "dm_core", "elbi", "iatu",
|
||||
"conf", "mhi", "rumi";
|
||||
qcom,target-link-speed = <0x1>;
|
||||
qcom,link-check-max-count = <200>; /* 1 sec */
|
||||
qcom,no-l1-supported;
|
||||
qcom,no-l1ss-supported;
|
||||
qcom,no-aux-clk-sync;
|
||||
};
|
||||
|
||||
pcie2: qcom,pcie@1c10000 {
|
||||
status = "disabled";
|
||||
reg = <0x01c10000 0x4000>,
|
||||
<0x1c16000 0x2000>,
|
||||
<0x6c000000 0xf1d>,
|
||||
<0x6c000f20 0xa8>,
|
||||
<0x6c001000 0x1000>,
|
||||
<0x6c100000 0x100000>,
|
||||
<0x01c14000 0x1000>;
|
||||
reg-names = "parf", "phy", "dm_core", "elbi", "iatu",
|
||||
"conf", "mhi";
|
||||
qcom,target-link-speed = <0x1>;
|
||||
qcom,link-check-max-count = <200>;
|
||||
qcom,no-l1-supported;
|
||||
qcom,no-l1ss-supported;
|
||||
qcom,no-aux-clk-sync;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_se1_2uart {
|
||||
qcom,rumi_platform;
|
||||
};
|
||||
|
||||
@@ -652,6 +652,7 @@
|
||||
#include "ipcc-test-sdxpinn.dtsi"
|
||||
#include "sdxpinn-regulators.dtsi"
|
||||
#include "sdxpinn-pinctrl.dtsi"
|
||||
#include "sdxpinn-pcie.dtsi"
|
||||
#include "sdxpinn-qupv3.dtsi"
|
||||
|
||||
&qupv3_se1_2uart {
|
||||
|
||||
Reference in New Issue
Block a user