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dt-bindings: cpuss-sleep-stats: Add support for v2 compatible

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For Quad core targets, read address of counter registers varies.

This adds new v2 compatible since some devices may have
different offsets to read cpuss sleep stats.

Change-Id: I5a6ad8054d808001526bd84146c767dee0f4fe13
This commit is contained in:
Tushar Nimkar
2022-02-13 11:27:12 +05:30
committed by Gerrit - the friendly Code Review server
parent 922cd3f778
commit 986c3e8416
1 changed files with 13 additions and 2 deletions
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15
bindings/soc/qcom/cpuss-sleep-stats.yaml
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@@ -18,7 +18,8 @@ description:
properties:
compatible:
enum:
- cpuss-sleep-stats
- qcom,cpuss-sleep-stats
- qcom,cpuss-sleep-stats-v2
reg:
maxItems: 10
@@ -29,7 +30,7 @@ reguired:
- reg-names
- num-cpus
example:
examples:
- |
cpuss-sleep-stats@18000054 {
compatible = "qcom,cpuss-sleep-stats";
@@ -44,3 +45,13 @@ example:
"l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
num-cpus = <8>;
};
- |
cpuss-sleep-stats@17800054 {
compatible = "qcom,cpuss-sleep-stats-v2";
reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
<0x17830054 0x4>, <0x17880098 0x4>, <0x178C0000 0x10000>;
reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
"seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
"l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
num-cpus = <4>;
};