mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-01-30 03:31:36 +00:00
Merge commit 'cb7a441f5e079fc57cd869e0d92359f6346f7fe9' of https://github.com/MotorolaMobilityLLC/kernel-display-devicetree into HEAD
* github.com:MotorolaMobilityLLC/kernel-display-devicetree: ARM: dts: msm: update UBWC version for kalama ARM: dts: msm: Enable HDR in 120hz & 90hz vtdr6130 panel on crow ARM: dts: msm: Enable PU for 120hz VTDR6130 panel on Crow ARM: dts: msm: update dma addr pool for display for crow target ARM: dts: msm: Update power ON/OFF sequence of vtdr6130 panel on Crow ARM: dts: msm: add ramdump display region for crow ARM: dts: msm: Update power ON/OFF sequence of vtdr6130 panel on Crow ARM: dts: qcom: add panel information for ECM driver for crow ARM: dts: msm: add ramdump display region for crow ARM: dts: msm: update default panel to vtdr6130 120hz on Crow IDPS ARM: dts: msm: change to enable dp on crow target ARM: dts: msm: reserve memory region for continuous splash ARM: dts: msm: update display topology to 221 for vtdr6130 panel on Crow ARM: dts: msm: enable sde rscc on crow target ARM: dts: msm: enable ulps for vtdr6130 120hz panel on crow ARM: dts: msm: change to enable dp on crow target ARM: dts: msm: update display topology to 221 for vtdr6130 panel on Crow ARM: dts: msm: reserve memory region for continuous splash ARM: dts: msm: remove unsupported timings from cmd sim panels on crow ARM: dts: msm: update display reset gpio for Crow target ARM: dts: msm: update default panel to vtdr6130 command for Crow ARM: dts: msm: update display reset gpio for Crow target ARM: dts: msm: add display support for crow IDPS platform ARM: dts: msm: remove DSI split link support ARM: dts: msm: update max low/high bandwidth for crow target ARM: dts: msm: update QoS table for crow target ARM: dts: msm: add display support for crow IDPS platform ARM: dts: msm: add 120hz 90hz vtdr panel support in crow target ARM: dts: msm: enable vtdr6130 panel features on Crow ARM: dts: msm: update max voltage of phy supply with pmic max value ARM: dts: msm: add trustedvm display platform overlay for crow target ARM: dts: msm: Add DP node for crow target ARM: dts: msm: add trusted vm dt changes for crow ARM: dts: msm: add support for Kalama RCM platform ARM: dts: msm: enable compilation of display platforms for crow target ARM: dts: msm: add link_parent clock in DP ARM: dts: msm: enable touch support for crow target ARM: dts: msm: add display dt node for crow target ARM: dts: msm: add display platform overlay for crow target ARM: dts: msm: enable DFPS for sharp QHD plus video mode panel on Kalama ARM: dts: msm: add support for Kalama SoC variant ARM: dts: msm: correct typo of qcom,bl-dsc-cmd-state property name bindings: correct typo in qcom,bl-dsc-cmd-state property name ARM: dts: msm: add support for hdk kalama target ARM: dts: msm: add ipcc dpu client physical id on kalama ARM: dts: msm: Add display device tree support for Kalama+sdxpinn Change-Id: I6e042bdf7f864f71efc0da81e7d8a858e67a9fe2
This commit is contained in:
Bruno Martins
@@ -22,6 +22,23 @@ dtbo-$(CONFIG_ARCH_KALAMA) += display/trustedvm-kalama-sde-display-mtp-overlay.d
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display/trustedvm-kalama-sde-display-atp-overlay.dtbo
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endif
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ifneq ($(CONFIG_ARCH_QTI_VM), y)
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dtbo-$(CONFIG_ARCH_CROW) += display/crow-sde.dtbo \
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display/crow-sde-display-idp-overlay.dtbo \
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display/crow-sde-display-idp-wcd-overlay.dtbo \
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display/crow-sde-display-atp-overlay.dtbo \
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display/crow-sde-display-rumi-overlay.dtbo \
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display/crow-sde-display-qrd-overlay.dtbo \
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display/crow-sde-display-idps-overlay.dtbo \
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display/crow-sde-display-idps-wcd-overlay.dtbo
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else
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dtbo-$(CONFIG_ARCH_CROW) += display/trustedvm-crow-sde-display-idp-overlay.dtbo \
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display/trustedvm-crow-sde-display-idp-wcd-overlay.dtbo \
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display/trustedvm-crow-sde-display-atp-overlay.dtbo \
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display/trustedvm-crow-sde-display-rumi-overlay.dtbo \
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display/trustedvm-crow-sde-display-qrd-overlay.dtbo
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endif
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ifeq ($(CONFIG_ARCH_SA8155), y)
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dtbo-y += display/sa8155-adp-star-display.dtbo
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endif
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@@ -260,7 +260,7 @@ Optional properties:
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255 = default value.
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- qcom,mdss-dsi-bl-inverted-dbv: A boolean to specify whether to invert the display brightness value.
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When this boolean is set, will inverted display brightness value.
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- qcom,bl-dsc-cmd-state: String that specifies the ctrl state for sending dcs brightness commands.
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- qcom,bl-dcs-cmd-state: String that specifies the ctrl state for sending dcs brightness commands.
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"dsi_hs_mode" = DSI high speed mode (default)
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"dsi_lp_mode" = DSI low power mode
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If the string was not set, dsi_hs_mode will be set as default mode.
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@@ -471,24 +471,30 @@ Optional properties:
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- qcom,sde-downscaling-prefill-lines: A u32 value indicates the latency of downscaling in lines.
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- qcom,sde-max-per-pipe-bw-kbps: Array of u32 value indicates the max per pipe bandwidth in Kbps.
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- qcom,sde-amortizable-threshold: This value indicates the min for traffic shaping in lines.
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- qcom,sde-vbif-qos-rt-remap: This u32 array is used to program vbif qos remapper register
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priority for realtime clients. First 8 entries are for rp_remap and
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the next 8 entries are for lvl_remap.
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- qcom,sde-vbif-qos-nrt-remap: This u32 array is used to program vbif qos remapper register
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priority for non-realtime clients. First 8 entries are for rp_remap and
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the next 8 entries are for lvl_remap.
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- qcom,sde-ddr-type: A u32 array indicates per pipe bandwidth and vbif qos
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configurations for different ddr types.
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- qcom,sde-vbif-qos-rt-remap: This u32 array is used to program the target vbif qos remapper
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register priority for realtime clients based on ddr-type.
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First 8 entries are for rp_remap and the next 8 entries are
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for lvl_remap.
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- qcom,sde-vbif-qos-nrt-remap: This u32 array is used to program the target vbif qos remapper
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register priority for non-realtime clients based on ddr-type.
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First 8 entries are for rp_remap and the next 8 entries are
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for lvl_remap.
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- qcom,sde-vbif-qos-cwb-remap: This u32 array is used to program vbif qos remapper register
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priority for concurrent writeback clients. First 8 entries are
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priority for concurrent writeback clients based on ddr-type.
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First 8 entries are for rp_remap and the next 8 entries are
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for lvl_remap.
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- qcom,sde-vbif-qos-lutdma-remap: This u32 array is used to program vbif qos remapper
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register priority for lutdma client based on ddr-type.
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First 8 entries are for rp_remap and the next 8 entries are
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for lvl_remap.
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- qcom,sde-vbif-qos-cnoc-remap: This u32 array is used to program vbif qos remapper register
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priority for cnoc clients based on ddr-type. First 8 entries are
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for rp_remap and the next 8 entries are for lvl_remap.
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- qcom,sde-vbif-qos-lutdma-remap: This u32 array is used to program vbif qos remapper register
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priority for lutdma client. First 8 entries are for rp_remap and
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the next 8 entries are for lvl_remap.
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- qcom,sde-vbif-qos-cnoc-remap: This u32 array is used to program vbif qos remapper register
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priority for cnoc clients. First 8 entries are for rp_remap and
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the next 8 entries are for lvl_remap.
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- qcom,sde-vbif-qos-offline-wb-remap: This u32 array is used to program vbif qos remapper register
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priority for offline-wb clients. First 8 entries are for rp_remap
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and the next 8 entries are for lvl_remap.
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priority for offline-wb clients based on ddr-type. First 8 entries
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are for rp_remap and the next 8 entries are for lvl_remap.
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- qcom,sde-qos-refresh-rates: This u32 array indicates danger, safe and creq luts
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qos configuration for different refresh rates.
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- qcom,sde-danger-lut: This u32 array of 16 cell property, with a format of
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@@ -513,6 +519,9 @@ Optional properties:
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silver or gold or gold+.
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- qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec.
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- qcom,sde-qos-cpu-irq-latency: A u32 value indicating desired PM QoS CPU irq latency in usec.
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- qcom,sde-ipcc-protocol-id: A u32 value indicating ipcc protocol id used for hw fencing feature.
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- qcom,sde-ipcc-client-dpu-phys-id: A u32 value indicating ipcc physical client id of dpu used
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for ipcc registers access.
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- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline
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rotation.
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- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin,
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@@ -831,6 +840,9 @@ Example:
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qcom,sde-qos-cpu-dma-latency = <300>;
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qcom,sde-qos-cpu-irq-latency = <300>;
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qcom,sde-ipcc-protocol-id = <0x2>;
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qcom,sde-ipcc-client-dpu-phys-id = <0x19>;
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qcom,sde-vbif-off = <0 0>;
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qcom,sde-vbif-id = <0 1>;
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qcom,sde-vbif-default-ot-rd-limit = <32>;
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377
qcom/display/display/crow-sde-common.dtsi
Normal file
377
qcom/display/display/crow-sde-common.dtsi
Normal file
@@ -0,0 +1,377 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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&soc {
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mdss_mdp: qcom,mdss_mdp@ae00000 {
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compatible = "qcom,sde-kms";
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reg = <0x0ae00000 0x84000>,
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<0x0aeb0000 0x2008>,
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<0x0aeac000 0x800>;
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reg-names = "mdp_phys",
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"vbif_phys",
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"regdma_phys";
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/* interrupt config */
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#cooling-cells = <2>;
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/* hw blocks */
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qcom,sde-off = <0x1000>;
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qcom,sde-len = <0x488>;
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qcom,sde-ctl-off = <0x16000 0x17000 0x18000
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0x19000>;
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qcom,sde-ctl-size = <0x290>;
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qcom,sde-ctl-display-pref = "primary", "none", "none",
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"none";
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qcom,sde-mixer-off = <0x45000 0x46000 0x47000
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0x48000
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0x0f0f 0x0f0f>;
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qcom,sde-mixer-size = <0x400>;
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qcom,sde-mixer-display-pref = "primary", "primary", "none",
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"none", "none", "none";
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qcom,sde-mixer-dcwb-pref = "none", "none", "none", "none",
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"dcwb", "dcwb";
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qcom,sde-dspp-top-off = <0x1300>;
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qcom,sde-dspp-top-size = <0x80>;
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qcom,sde-dspp-off = <0x55000 0x57000>;
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qcom,sde-dspp-size = <0x1800>;
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qcom,sde-dspp-rc-version = <0x00010001>;
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qcom,sde-dspp-rc-off = <0x15800 0x14800>;
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qcom,sde-dspp-rc-size = <0x38>;
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qcom,sde-dspp-rc-mem-size = <2720>;
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qcom,sde-dspp-rc-min-region-width = <20>;
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qcom,sde-dest-scaler-top-off = <0x00061000>;
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qcom,sde-dest-scaler-top-size = <0x1c>;
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qcom,sde-dest-scaler-off = <0x0 0x1000>;
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qcom,sde-dest-scaler-size = <0x800>;
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qcom,sde-wb-off = <0x66000>;
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qcom,sde-wb-size = <0x2c8>;
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qcom,sde-wb-xin-id = <6>;
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qcom,sde-wb-id = <2>;
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qcom,sde-intf-off = <0x35000 0x36000
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0x38000 0x3a000>;
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qcom,sde-intf-size = <0x300>;
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qcom,sde-intf-type = "dp", "dsi", "dp", "dp";
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qcom,sde-intf-tear-irq-off = <0 0x36800 0 0>;
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qcom,sde-pp-off = <0x6a000 0x6b000 0x6c000 0x6d000
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0x67000 0x67400>;
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qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>;
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qcom,sde-pp-size = <0x4>;
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qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>;
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qcom,sde-merge-3d-off = <0x4f000 0x50000 0x67700>;
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qcom,sde-merge-3d-size = <0x8>;
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qcom,sde-pp-cwb = <0x0 0x0 0x0 0x0 0x1 0x1>;
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qcom,sde-cdm-off = <0x7a200>;
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qcom,sde-cdm-size = <0x220>;
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qcom,sde-dsc-off = <0x81000 0x81000>;
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qcom,sde-dsc-size = <0x4>;
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qcom,sde-dsc-pair-mask = <2 1>;
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qcom,sde-dsc-hw-rev = "dsc_1_2";
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qcom,sde-dsc-enc = <0x100 0x200>;
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qcom,sde-dsc-enc-size = <0x9c>;
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qcom,sde-dsc-ctl = <0xF00 0xF80>;
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qcom,sde-dsc-ctl-size = <0x24>;
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qcom,sde-dsc-native422-supp = <1 1>;
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qcom,sde-dither-off = <0xe0 0xe0 0xe0
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0xe0 0xe0 0xe0>;
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qcom,sde-cwb-dither = <0x0 0x0 0x0 0x0 0x1 0x1>;
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qcom,sde-dither-version = <0x00020000>;
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qcom,sde-dither-size = <0x20>;
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qcom,sde-sspp-type = "vig", "vig",
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"dma", "dma", "dma", "dma";
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qcom,sde-sspp-off = <0x5000 0x7000
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0x25000 0x27000 0x29000 0x2b000>;
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qcom,sde-sspp-src-size = <0x344>;
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qcom,sde-sspp-xin-id = <0 4 1 5 9 13>;
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qcom,sde-sspp-excl-rect = <1 1 1 1 1 1>;
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qcom,sde-sspp-smart-dma-priority = <5 6 1 2 3 4>;
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qcom,sde-smart-dma-rev = "smart_dma_v2p5";
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qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>;
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qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
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0xb0 0xc8 0xe0 0xf8 0x110>;
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qcom,sde-max-per-pipe-bw-kbps = <4300000 4300000
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4300000 4300000
|
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4300000 4300000>;
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|
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/* offsets are relative to "mdp_phys + qcom,sde-off */
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qcom,sde-sspp-clk-ctrl =
|
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<0x4330 0>, <0x6330 0>,
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<0x24330 0>, <0x26330 0>, <0x28330 0>, <0x2a330 0>;
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qcom,sde-sspp-clk-status =
|
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<0x4334 0>, <0x6334 0>,
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<0x24334 0>, <0x26334 0>, <0x28334 0>, <0x2a334 0>;
|
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qcom,sde-sspp-csc-off = <0x1a00>;
|
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qcom,sde-csc-type = "csc-10bit";
|
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qcom,sde-qseed-sw-lib-rev = "qseedv3lite";
|
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qcom,sde-qseed-scalar-version = <0x3002>;
|
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qcom,sde-sspp-qseed-off = <0xa00>;
|
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qcom,sde-mixer-linewidth = <2560>;
|
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qcom,sde-sspp-linewidth = <4096>;
|
||||
qcom,sde-vig-sspp-linewidth = <5120>;
|
||||
qcom,sde-wb-linewidth = <4096>;
|
||||
qcom,sde-dsc-linewidth = <2560>;
|
||||
qcom,sde-max-dest-scaler-input-linewidth = <2048>;
|
||||
qcom,sde-max-dest-scaler-output-linewidth = <2560>;
|
||||
qcom,sde-wb-linewidth-linear = <5120>;
|
||||
qcom,sde-mixer-blendstages = <0xb>;
|
||||
qcom,sde-highest-bank-bit = <0x8 0x2>,
|
||||
<0x7 0x1>;
|
||||
qcom,sde-ubwc-version = <0x40000002>;
|
||||
qcom,sde-ubwc-swizzle = <0x6>;
|
||||
qcom,sde-ubwc-bw-calc-version = <0x1>;
|
||||
qcom,sde-ubwc-static = <0x1>;
|
||||
qcom,sde-macrotile-mode = <0x1>;
|
||||
qcom,sde-smart-panel-align-mode = <0xc>;
|
||||
qcom,sde-panic-per-pipe;
|
||||
qcom,sde-has-cdp;
|
||||
qcom,sde-has-src-split;
|
||||
qcom,sde-pipe-order-version = <0x1>;
|
||||
qcom,sde-has-dim-layer;
|
||||
qcom,sde-has-dest-scaler;
|
||||
qcom,sde-max-trusted-vm-displays = <1>;
|
||||
|
||||
qcom,sde-max-bw-low-kbps = <8000000>;
|
||||
qcom,sde-max-bw-high-kbps = <12600000>;
|
||||
qcom,sde-min-core-ib-kbps = <2500000>;
|
||||
qcom,sde-min-llcc-ib-kbps = <0>;
|
||||
qcom,sde-min-dram-ib-kbps = <800000>;
|
||||
qcom,sde-dram-channels = <2>;
|
||||
qcom,sde-num-nrt-paths = <0>;
|
||||
qcom,sde-num-ddr-channels = <2>;
|
||||
|
||||
qcom,sde-dspp-spr-off = <0x15400 0x14400>;
|
||||
qcom,sde-dspp-spr-size = <0x100>;
|
||||
qcom,sde-dspp-spr-version = <0x00010000>;
|
||||
|
||||
qcom,sde-dspp-demura-off = <0x15600 0x14600>;
|
||||
qcom,sde-dspp-demura-size = <0xe4>;
|
||||
qcom,sde-dspp-demura-version = <0x00010000>;
|
||||
|
||||
qcom,sde-lm-noise-off = <0x320>;
|
||||
qcom,sde-lm-noise-version = <0x00010000>;
|
||||
|
||||
qcom,sde-uidle-off = <0x80000>;
|
||||
qcom,sde-uidle-size = <0x80>;
|
||||
|
||||
qcom,sde-vbif-off = <0>;
|
||||
qcom,sde-vbif-size = <0x1074>;
|
||||
qcom,sde-vbif-id = <0>;
|
||||
qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
|
||||
qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3 3 3>;
|
||||
|
||||
qcom,sde-vbif-default-ot-rd-limit = <40>;
|
||||
qcom,sde-vbif-default-ot-wr-limit = <32>;
|
||||
qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>;
|
||||
|
||||
qcom,sde-ddr-type = <0x8 0x7>;
|
||||
qcom,sde-vbif-qos-rt-remap = <4 4 5 5 6 6 6 6 4 4 5 5 6 6 6 6>,
|
||||
<4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>;
|
||||
qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>,
|
||||
<3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>;
|
||||
qcom,sde-vbif-qos-cwb-remap = <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>,
|
||||
<4 4 4 4 4 5 6 6 4 4 4 4 4 5 6 6>;
|
||||
qcom,sde-vbif-qos-lutdma-remap = <4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>,
|
||||
<4 4 5 5 5 5 6 6 4 4 5 5 5 5 6 6>;
|
||||
qcom,sde-vbif-qos-offline-wb-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>,
|
||||
<3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>;
|
||||
qcom,sde-vbif-qos-cnoc-remap = <3 3 4 4 5 5 5 5 3 3 3 3 3 3 3 3>,
|
||||
<3 3 4 4 5 5 5 5 3 3 3 3 3 3 3 3>;
|
||||
|
||||
qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0xffff 0xffff 0xffff 0xffff 0x0 0x0>;
|
||||
|
||||
qcom,sde-safe-lut = <0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff 0x0001 0x0001
|
||||
0x03ff 0x03ff 0xff00 0xfff0 0xff00 0xfff0 0xffff 0xffff>;
|
||||
|
||||
qcom,sde-creq-lut = <0x00112233 0x44556666 0x00112233 0x66666666
|
||||
0x00112233 0x44556666 0x00112233 0x66666666
|
||||
0x0 0x0 0x0 0x0
|
||||
0x77776666 0x66666540 0x77776666 0x66666540
|
||||
0x77776541 0x0 0x77776541 0x0
|
||||
0x00112233 0x44556666 0x00112233 0x66666666
|
||||
0x00112233 0x44556666 0x00112233 0x66666666
|
||||
0x0 0x0 0x0 0x0>;
|
||||
|
||||
qcom,sde-cdp-setting = <1 1>, <1 0>;
|
||||
|
||||
qcom,sde-qos-cpu-mask = <0x3>;
|
||||
qcom,sde-qos-cpu-mask-performance = <0xf>;
|
||||
qcom,sde-qos-cpu-dma-latency = <300>;
|
||||
qcom,sde-qos-cpu-irq-latency = <300>;
|
||||
|
||||
/* offsets are relative to "mdp_phys + qcom,sde-off */
|
||||
qcom,sde-reg-dma-off = <0 0x400>;
|
||||
qcom,sde-reg-dma-id = <0 1>;
|
||||
qcom,sde-reg-dma-version = <0x00020000>;
|
||||
qcom,sde-reg-dma-trigger-off = <0x119c>;
|
||||
qcom,sde-reg-dma-xin-id = <7>;
|
||||
qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
|
||||
|
||||
qcom,sde-secure-sid-mask = <0x0001c01>;
|
||||
|
||||
qcom,sde-reg-bus,vectors-KBps = <0 0>,
|
||||
<0 57000>,
|
||||
<0 590000>,
|
||||
<0 1190000>;
|
||||
|
||||
qcom,sde-sspp-vig-blocks {
|
||||
vcm@0 {
|
||||
cell-index = <0>;
|
||||
qcom,sde-vig-top-off = <0xa00>;
|
||||
qcom,sde-vig-csc-off = <0x1a00>;
|
||||
qcom,sde-vig-qseed-off = <0xa00>;
|
||||
qcom,sde-vig-qseed-size = <0xe0>;
|
||||
qcom,sde-vig-gamut = <0x1d00 0x00060001>;
|
||||
qcom,sde-vig-igc = <0x1d00 0x00060000>;
|
||||
qcom,sde-vig-inverse-pma;
|
||||
qcom,sde-fp16-igc = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-unmult = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-gc = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-csc = <0x200 0x00010000>;
|
||||
};
|
||||
|
||||
vcm@1 {
|
||||
cell-index = <1>;
|
||||
qcom,sde-fp16-igc = <0x280 0x00010000>;
|
||||
qcom,sde-fp16-unmult = <0x280 0x00010000>;
|
||||
qcom,sde-fp16-gc = <0x280 0x00010000>;
|
||||
qcom,sde-fp16-csc = <0x280 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,sde-sspp-dma-blocks {
|
||||
dgm@0 {
|
||||
cell-index = <0>;
|
||||
qcom,sde-dma-top-off = <0x800>;
|
||||
qcom,sde-dma-igc = <0xa00 0x00050000>;
|
||||
qcom,sde-dma-gc = <0xc00 0x00050000>;
|
||||
qcom,sde-dma-inverse-pma;
|
||||
qcom,sde-dma-csc-off = <0x800>;
|
||||
qcom,sde-fp16-igc = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-unmult = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-gc = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-csc = <0x200 0x00010000>;
|
||||
};
|
||||
|
||||
dgm@1 {
|
||||
cell-index = <1>;
|
||||
qcom,sde-dma-igc = <0x1a00 0x00050000>;
|
||||
qcom,sde-dma-gc = <0xc00 0x00050000>;
|
||||
qcom,sde-dma-inverse-pma;
|
||||
qcom,sde-dma-csc-off = <0x1800>;
|
||||
qcom,sde-fp16-igc = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-unmult = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-gc = <0x200 0x00010000>;
|
||||
qcom,sde-fp16-csc = <0x200 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,sde-dspp-blocks {
|
||||
qcom,sde-dspp-igc = <0x1260 0x00040000>;
|
||||
qcom,sde-dspp-hsic = <0x800 0x00010007>;
|
||||
qcom,sde-dspp-memcolor = <0x880 0x00010007>;
|
||||
qcom,sde-dspp-hist = <0x800 0x00010007>;
|
||||
qcom,sde-dspp-sixzone = <0x900 0x00020000>;
|
||||
qcom,sde-dspp-vlut = <0xa00 0x00010008>;
|
||||
qcom,sde-dspp-gamut = <0x1000 0x00040003>;
|
||||
qcom,sde-dspp-pcc = <0x1700 0x00040000>;
|
||||
qcom,sde-dspp-gc = <0x17c0 0x00010008>;
|
||||
qcom,sde-dspp-dither = <0x82c 0x00010007>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
|
||||
compatible = "qcom,dsi-ctrl-hw-v2.7";
|
||||
label = "dsi-ctrl-0";
|
||||
cell-index = <0>;
|
||||
frame-threshold-time-us = <800>;
|
||||
reg = <0xae94000 0x1000>,
|
||||
<0xaf0f000 0x4>,
|
||||
<0x0ae36000 0x300>;
|
||||
reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <4 0>;
|
||||
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1200000>;
|
||||
qcom,supply-enable-load = <16800>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae95500 {
|
||||
compatible = "qcom,dsi-phy-v5.2";
|
||||
label = "dsi-phy-0";
|
||||
cell-index = <0>;
|
||||
#clock-cells = <1>;
|
||||
reg = <0xae95000 0xa00>,
|
||||
<0xae95500 0x400>,
|
||||
<0xae94200 0xa0>;
|
||||
reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
|
||||
pll-label = "dsi_pll_4nm";
|
||||
|
||||
qcom,platform-strength-ctrl = [55 03
|
||||
55 03
|
||||
55 03
|
||||
55 03
|
||||
55 00];
|
||||
qcom,platform-lane-config = [00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 0a 0a
|
||||
00 00 8a 8a];
|
||||
qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage = <880000>;
|
||||
qcom,supply-max-voltage = <912000>;
|
||||
qcom,supply-enable-load = <98400>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsi_pll_codes_data:dsi_pll_codes {
|
||||
reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
|
||||
0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
|
||||
label = "dsi_pll_codes";
|
||||
};
|
||||
};
|
||||
11
qcom/display/display/crow-sde-display-atp-overlay.dts
Normal file
11
qcom/display/display/crow-sde-display-atp-overlay.dts
Normal file
@@ -0,0 +1,11 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "crow-sde-display-atp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Crow ATP";
|
||||
compatible = "qcom,crow-atp", "qcom,crow", "qcom,atp";
|
||||
qcom,msm-id = <608 0x10000>;
|
||||
qcom,board-id = <33 0>;
|
||||
};
|
||||
25
qcom/display/display/crow-sde-display-atp.dtsi
Normal file
25
qcom/display/display/crow-sde-display-atp.dtsi
Normal file
@@ -0,0 +1,25 @@
|
||||
#include "crow-sde-display-idp.dtsi"
|
||||
|
||||
&qupv3_se0_i2c {
|
||||
goodix-berlin@5d {
|
||||
panel = <&dsi_vtdr6130_amoled_cmd
|
||||
&dsi_vtdr6130_amoled_video
|
||||
&dsi_vtdr6130_amoled_120hz_cmd
|
||||
&dsi_vtdr6130_amoled_120hz_video
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video
|
||||
&dsi_vtdr6130_amoled_90hz_video>;
|
||||
};
|
||||
};
|
||||
|
||||
&spmi_bus {
|
||||
pm7550ba_amoled_ecm {
|
||||
display-panels = <&dsi_vtdr6130_amoled_cmd
|
||||
&dsi_vtdr6130_amoled_video
|
||||
&dsi_vtdr6130_amoled_120hz_cmd
|
||||
&dsi_vtdr6130_amoled_120hz_video
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video
|
||||
&dsi_vtdr6130_amoled_90hz_video>;
|
||||
};
|
||||
};
|
||||
560
qcom/display/display/crow-sde-display-common.dtsi
Normal file
560
qcom/display/display/crow-sde-display-common.dtsi
Normal file
@@ -0,0 +1,560 @@
|
||||
#include "dsi-panel-sim-cmd.dtsi"
|
||||
#include "dsi-panel-sim-video.dtsi"
|
||||
#include "dsi-panel-sim-dsc375-cmd.dtsi"
|
||||
#include "dsi-panel-sim-dsc-10bit-cmd.dtsi"
|
||||
#include "dsi-panel-sim-cmd-au.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-video.dtsi"
|
||||
#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-qsync-dsc-fhd-plus-144hz-video.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-cmd.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-120hz-video.dtsi"
|
||||
#include "dsi-panel-vtdr6130-dsc-fhd-plus-90hz-video.dtsi"
|
||||
|
||||
#include "crow-sde-display-pinctrl.dtsi"
|
||||
|
||||
&soc {
|
||||
dsi_panel_pwr_supply_sim: dsi_panel_pwr_supply_sim {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "dummy";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <200000>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
};
|
||||
|
||||
dsi_panel_pwr_supply: dsi_panel_pwr_supply {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,panel-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vddio";
|
||||
qcom,supply-min-voltage = <1800000>;
|
||||
qcom,supply-max-voltage = <1800000>;
|
||||
qcom,supply-enable-load = <200000>;
|
||||
qcom,supply-disable-load = <80>;
|
||||
qcom,supply-post-on-sleep = <20>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@1 {
|
||||
reg = <1>;
|
||||
qcom,supply-name = "vci";
|
||||
qcom,supply-min-voltage = <3000000>;
|
||||
qcom,supply-max-voltage = <3000000>;
|
||||
qcom,supply-enable-load = <10000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
qcom,supply-post-on-sleep = <1>;
|
||||
qcom,supply-post-off-sleep = <2>;
|
||||
};
|
||||
|
||||
qcom,panel-supply-entry@2 {
|
||||
reg = <2>;
|
||||
qcom,supply-name = "vdd";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1200000>;
|
||||
qcom,supply-enable-load = <299000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
qcom,supply-post-on-sleep = <0>;
|
||||
qcom,supply-post-off-sleep = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi: qcom,dsi-display-primary {
|
||||
compatible = "qcom,dsi-display";
|
||||
label = "primary";
|
||||
|
||||
qcom,dsi-ctrl = <&mdss_dsi0>;
|
||||
qcom,dsi-phy = <&mdss_dsi_phy0>;
|
||||
|
||||
pinctrl-names = "panel_active", "panel_suspend";
|
||||
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
|
||||
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
|
||||
|
||||
qcom,platform-te-gpio = <&tlmm 122 0>;
|
||||
qcom,panel-te-source = <0>;
|
||||
|
||||
qcom,mdp = <&mdss_mdp>;
|
||||
qcom,demura-panel-id = <0x0122e700 0x00000471>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/* PHY TIMINGS REVISION YL with reduced margins */
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,dsi-dyn-clk-enable;
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
timing@1 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
timing@2 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
timing@3 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <813936000 818175250 822414500>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,dsi-supported-dfps-list = <144 120 90 60>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
||||
|
||||
qcom,dsi-dyn-clk-enable;
|
||||
qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp";
|
||||
|
||||
qcom,qsync-enable;
|
||||
qcom,dsi-supported-qsync-min-fps-list = <80 70 60 50>;
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
qcom,dsi-dyn-clk-list = <847480320 844537680 841595040>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,dsi-supported-dfps-list = <120 90 60>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 15 14 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_90hz_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 13 1e 05
|
||||
05 06 02 04 00 12 0a];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,esd-check-enabled;
|
||||
qcom,mdss-dsi-panel-status-check-mode = "reg_read";
|
||||
qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
|
||||
qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-panel-status-value = <0x9c>;
|
||||
qcom,mdss-dsi-panel-status-read-length = <1>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-enabled;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 17 22 07
|
||||
07 08 02 04 00 19 0c];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,poms-align-panel-vsync;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* WQHD 60FPS cmd-vid mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
07 07 02 04 00 16 0c];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@1 { /* WQHD 60FPS vid mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
07 07 02 04 00 16 0c];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@2 { /* FHD+ 60FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 25 0a 0a 1b 24 0a
|
||||
0a 0a 02 04 00 1f 0f];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@3 { /* HD 60FPS cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 29 0a 0b 1b 26 0a
|
||||
0b 0a 02 04 00 21 10];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@4 { /* FHD+ 90FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e
|
||||
0f 0d 02 04 00 2d 13];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@5 { /* FHD+ 180 FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 69 1d 1d 35 2f 1b
|
||||
1d 18 02 04 00 51 21];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
/delete-node/ timing@6; /* FHD+ 240 FPS cmd mode*/
|
||||
|
||||
timing@7 { /* FHD+ 120FPS cmd mode*/
|
||||
cell-index = <6>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 4a 13 14 28 24 12
|
||||
14 11 02 04 00 39 18];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@8 { /* FHD+ 1FPS cmd mode*/
|
||||
cell-index = <7>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01
|
||||
00 01 02 04 00 05 05];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@9 { /* FHD+ 5FPS cmd mode*/
|
||||
cell-index = <8>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 06 00 00 0d 1a 01
|
||||
00 01 02 04 00 06 05];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@10 { /* FHD+ 10FPS cmd mode*/
|
||||
cell-index = <9>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01
|
||||
01 01 02 04 00 07 06];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@11 { /* FHD+ 24FPS cmd mode*/
|
||||
cell-index = <10>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02
|
||||
01 01 02 04 00 08 06];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@12 { /* FHD+ 30FPS cmd mode*/
|
||||
cell-index = <11>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02
|
||||
02 01 02 04 00 09 07];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@13 { /* FHD+ 144FPS cmd mode*/
|
||||
cell-index = <12>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,mdss-dsi-panel-phy-timings = [01 05 01 01 03 03 01
|
||||
01 01 02 04 00 06 06];
|
||||
qcom,display-topology = <1 0 1>,
|
||||
<2 0 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* 1080p */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05
|
||||
05 06 02 04 00 13 0a];
|
||||
qcom,display-topology = <1 1 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@1 { /* qhd */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0c 02 02 10 1c 03
|
||||
03 02 02 04 00 0b 08];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* QHD 60fps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 14 1f 05
|
||||
05 06 02 04 00 13 0a];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@1 { /* FHD+ 60fps cmd mode */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0d 03 03 10 1d 03
|
||||
03 02 02 04 00 0c 08];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@2 { /* QHD 90fps */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1d 08 07 17 22 08
|
||||
08 08 02 04 00 19 0d];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>, /* dsc merge */
|
||||
<2 1 1>; /* 3d mux */
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@3 { /* FHD+ 180FPS cmd mode*/
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1f 08 07 18 16 08
|
||||
08 08 02 04 00 1a 0d];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
/delete-node/ timing@4; /* FHD+ 240FPS cmd mode*/
|
||||
|
||||
timing@5 { /* FHD+ 120FPS cmd mode*/
|
||||
cell-index = <4>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 14 13 06
|
||||
06 06 02 04 00 13 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@6 { /* FHD+ 1FPS cmd mode*/
|
||||
cell-index = <5>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 04 00 00 0d 18 01
|
||||
00 01 02 04 00 05 05];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@7 { /* FHD+ 10FPS cmd mode*/
|
||||
cell-index = <6>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 0d 1a 01
|
||||
01 01 02 04 00 07 06];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@8 { /* FHD+ 24FPS cmd mode*/
|
||||
cell-index = <7>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 09 01 01 0e 1b 02
|
||||
01 01 02 04 00 08 06];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@9 { /* FHD+ 30FPS cmd mode*/
|
||||
cell-index = <8>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 0e 1b 02
|
||||
02 01 02 04 00 09 07];
|
||||
qcom,display-topology = <1 1 1>,
|
||||
<2 2 1>;
|
||||
qcom,default-topology-index = <1>;
|
||||
};
|
||||
|
||||
timing@10 { /* FHD+ 90FPS cmd mode*/
|
||||
cell-index = <9>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 39 0f 0e 21 2a 0e
|
||||
0f 0d 02 04 00 2d 13];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
|
||||
timing@11 { /* FHD+ 144FPS cmd mode*/
|
||||
cell-index = <10>;
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 16 20 07
|
||||
06 07 02 04 00 16 0b];
|
||||
qcom,display-topology = <2 2 1>;
|
||||
qcom,default-topology-index = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
11
qcom/display/display/crow-sde-display-idp-overlay.dts
Normal file
11
qcom/display/display/crow-sde-display-idp-overlay.dts
Normal file
@@ -0,0 +1,11 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "crow-sde-display-idp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Crow IDP";
|
||||
compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp";
|
||||
qcom,msm-id = <608 0x10000>;
|
||||
qcom,board-id = <34 0>;
|
||||
};
|
||||
11
qcom/display/display/crow-sde-display-idp-wcd-overlay.dts
Normal file
11
qcom/display/display/crow-sde-display-idp-wcd-overlay.dts
Normal file
@@ -0,0 +1,11 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "crow-sde-display-idp-wcd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Crow IDP WCD";
|
||||
compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp";
|
||||
qcom,msm-id = <608 0x10000>;
|
||||
qcom,board-id = <34 1>, <34 3>;
|
||||
};
|
||||
5
qcom/display/display/crow-sde-display-idp-wcd.dtsi
Normal file
5
qcom/display/display/crow-sde-display-idp-wcd.dtsi
Normal file
@@ -0,0 +1,5 @@
|
||||
#include "crow-sde-display-idp.dtsi"
|
||||
|
||||
&sde_dp {
|
||||
qcom,dp-aux-switch = <&wcd_usbss>;
|
||||
};
|
||||
133
qcom/display/display/crow-sde-display-idp.dtsi
Normal file
133
qcom/display/display/crow-sde-display-idp.dtsi
Normal file
@@ -0,0 +1,133 @@
|
||||
#include "crow-sde-display.dtsi"
|
||||
|
||||
&sde_dp {
|
||||
qcom,dp-aux-switch = <&fsa4480>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_90hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>;
|
||||
};
|
||||
|
||||
&qupv3_se0_spi {
|
||||
goodix-berlin@0 {
|
||||
panel = <&dsi_vtdr6130_amoled_cmd
|
||||
&dsi_vtdr6130_amoled_video
|
||||
&dsi_vtdr6130_amoled_120hz_cmd
|
||||
&dsi_vtdr6130_amoled_120hz_video
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video
|
||||
&dsi_vtdr6130_amoled_90hz_video>;
|
||||
};
|
||||
};
|
||||
|
||||
&spmi_bus {
|
||||
pm7550ba_amoled_ecm {
|
||||
display-panels = <&dsi_vtdr6130_amoled_cmd
|
||||
&dsi_vtdr6130_amoled_video
|
||||
&dsi_vtdr6130_amoled_120hz_cmd
|
||||
&dsi_vtdr6130_amoled_120hz_video
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video
|
||||
&dsi_vtdr6130_amoled_90hz_video>;
|
||||
};
|
||||
};
|
||||
11
qcom/display/display/crow-sde-display-idps-overlay.dts
Normal file
11
qcom/display/display/crow-sde-display-idps-overlay.dts
Normal file
@@ -0,0 +1,11 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "crow-sde-display-idps.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Crow IDPS";
|
||||
compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp";
|
||||
qcom,msm-id = <608 0x10000>;
|
||||
qcom,board-id = <34 4>;
|
||||
};
|
||||
11
qcom/display/display/crow-sde-display-idps-wcd-overlay.dts
Normal file
11
qcom/display/display/crow-sde-display-idps-wcd-overlay.dts
Normal file
@@ -0,0 +1,11 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "crow-sde-display-idps-wcd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Crow IDPS WCD";
|
||||
compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp";
|
||||
qcom,msm-id = <608 0x10000>;
|
||||
qcom,board-id = <34 2>;
|
||||
};
|
||||
5
qcom/display/display/crow-sde-display-idps-wcd.dtsi
Normal file
5
qcom/display/display/crow-sde-display-idps-wcd.dtsi
Normal file
@@ -0,0 +1,5 @@
|
||||
#include "crow-sde-display-idps.dtsi"
|
||||
|
||||
&sde_dp {
|
||||
qcom,dp-aux-switch = <&wcd_usbss>;
|
||||
};
|
||||
165
qcom/display/display/crow-sde-display-idps.dtsi
Normal file
165
qcom/display/display/crow-sde-display-idps.dtsi
Normal file
@@ -0,0 +1,165 @@
|
||||
#include "crow-sde-display.dtsi"
|
||||
|
||||
&sde_dp {
|
||||
qcom,dp-aux-switch = <&fsa4480>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
/delete-property/ qcom,mdss-dsi-panel-clockrate;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
/delete-property/ qcom,mdss-dsi-panel-clockrate;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
/delete-property/ qcom,mdss-dsi-panel-clockrate;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
/delete-property/ qcom,mdss-dsi-panel-clockrate;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
/delete-property/ qcom,mdss-dsi-panel-clockrate;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
/delete-property/ qcom,mdss-dsi-panel-clockrate;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
/delete-property/ qcom,mdss-dsi-panel-clockrate;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_panel_au {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_90hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_120hz_cmd>;
|
||||
};
|
||||
|
||||
&qupv3_se0_spi {
|
||||
goodix-berlin@0 {
|
||||
panel = <&dsi_vtdr6130_amoled_cmd
|
||||
&dsi_vtdr6130_amoled_video
|
||||
&dsi_vtdr6130_amoled_120hz_cmd
|
||||
&dsi_vtdr6130_amoled_120hz_video
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video
|
||||
&dsi_vtdr6130_amoled_90hz_video>;
|
||||
};
|
||||
};
|
||||
|
||||
&spmi_bus {
|
||||
pm7550ba_amoled_ecm {
|
||||
display-panels = <&dsi_vtdr6130_amoled_cmd
|
||||
&dsi_vtdr6130_amoled_video
|
||||
&dsi_vtdr6130_amoled_120hz_cmd
|
||||
&dsi_vtdr6130_amoled_120hz_video
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video
|
||||
&dsi_vtdr6130_amoled_90hz_video>;
|
||||
};
|
||||
};
|
||||
58
qcom/display/display/crow-sde-display-pinctrl.dtsi
Normal file
58
qcom/display/display/crow-sde-display-pinctrl.dtsi
Normal file
@@ -0,0 +1,58 @@
|
||||
&tlmm {
|
||||
pmx_sde: pmx_sde {
|
||||
sde_dsi_active: sde_dsi_active {
|
||||
mux {
|
||||
pins = "gpio29";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio29";
|
||||
drive-strength = <8>; /* 8 mA */
|
||||
bias-disable = <0>; /* no pull */
|
||||
};
|
||||
};
|
||||
|
||||
sde_dsi_suspend: sde_dsi_suspend {
|
||||
mux {
|
||||
pins = "gpio29";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio29";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pmx_sde_te: pmx_sde_te {
|
||||
sde_te_active: sde_te_active {
|
||||
mux {
|
||||
pins = "gpio122";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio122";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
|
||||
sde_te_suspend: sde_te_suspend {
|
||||
mux {
|
||||
pins = "gpio122";
|
||||
function = "mdp_vsync";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio122";
|
||||
drive-strength = <2>; /* 2 mA */
|
||||
bias-pull-down; /* PULL DOWN */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
11
qcom/display/display/crow-sde-display-qrd-overlay.dts
Normal file
11
qcom/display/display/crow-sde-display-qrd-overlay.dts
Normal file
@@ -0,0 +1,11 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "crow-sde-display-qrd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Crow QRD";
|
||||
compatible = "qcom,crow-qrd", "qcom,crow", "qcom,qrd";
|
||||
qcom,msm-id = <608 0x10000>;
|
||||
qcom,board-id = <11 0>;
|
||||
};
|
||||
5
qcom/display/display/crow-sde-display-qrd.dtsi
Normal file
5
qcom/display/display/crow-sde-display-qrd.dtsi
Normal file
@@ -0,0 +1,5 @@
|
||||
#include "crow-sde-display-idp.dtsi"
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>;
|
||||
};
|
||||
11
qcom/display/display/crow-sde-display-rumi-overlay.dts
Normal file
11
qcom/display/display/crow-sde-display-rumi-overlay.dts
Normal file
@@ -0,0 +1,11 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "crow-sde-display-rumi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Crow RUMI";
|
||||
compatible = "qcom,crow-rumi", "qcom,crow", "qcom,rumi";
|
||||
qcom,msm-id = <608 0x10000>;
|
||||
qcom,board-id = <15 0>;
|
||||
};
|
||||
34
qcom/display/display/crow-sde-display-rumi.dtsi
Normal file
34
qcom/display/display/crow-sde-display-rumi.dtsi
Normal file
@@ -0,0 +1,34 @@
|
||||
#include "crow-sde-display.dtsi"
|
||||
|
||||
&mdss_mdp {
|
||||
qcom,sde-emulated-env;
|
||||
connectors = <&sde_dsi &smmu_sde_unsec &smmu_sde_sec &sde_wb>;
|
||||
};
|
||||
|
||||
&sde_dp {
|
||||
status="disabled";
|
||||
};
|
||||
&mdss_dsi0 {
|
||||
qcom,dsi-phy-isolation-enabled;
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_sim_vid>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
clock-names = "mdp_core_clk";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,dsi-select-clocks = "";
|
||||
qcom,mdss-dsi-te-using-wd;
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,dsi-select-clocks = "";
|
||||
/delete-property/ qcom,mdss-dsi-lane-3-state;
|
||||
/delete-property/ qcom,poms-align-panel-vsync;
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
|
||||
};
|
||||
127
qcom/display/display/crow-sde-display.dtsi
Normal file
127
qcom/display/display/crow-sde-display.dtsi
Normal file
@@ -0,0 +1,127 @@
|
||||
#include <dt-bindings/clock/qcom,dispcc-crow.h>
|
||||
#include "crow-sde-display-common.dtsi"
|
||||
|
||||
&soc {
|
||||
sde_wb: qcom,wb-display@0 {
|
||||
compatible = "qcom,wb-display";
|
||||
cell-index = <0>;
|
||||
label = "wb_display";
|
||||
};
|
||||
|
||||
disp_rdump_memory: disp_rdump_region@b8000000 {
|
||||
reg = <0xb8000000 0x00800000>;
|
||||
label = "disp_rdump_region";
|
||||
};
|
||||
};
|
||||
|
||||
&reserved_memory {
|
||||
splash_memory: splash_region {
|
||||
reg = <0x0 0xb8000000 0x0 0x02b00000>;
|
||||
label = "cont_splash_region";
|
||||
};
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
clocks = <&mdss_dsi_phy0 0>,
|
||||
<&mdss_dsi_phy0 1>,
|
||||
/*
|
||||
* Currently the dsi clock handles are under the dsi
|
||||
* controller DT node. As soon as the controller probe
|
||||
* finishes, the dispcc sync state can get called before
|
||||
* the dsi_display probe potentially disturbing the clock
|
||||
* votes for cont_splash use case. Hence we are no longer
|
||||
* protected by the component model in this case against the
|
||||
* disp cc sync state getting triggered after the dsi_ctrl
|
||||
* probe. To protect against this incorrect sync state trigger
|
||||
* add this dummy MDP clk vote handle to the dsi_display
|
||||
* DT node. Since the dsi_display driver does not parse
|
||||
* MDP clock nodes, no actual vote shall be added and this
|
||||
* change is done just to satisfy sync state requirements.
|
||||
*/
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>;
|
||||
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0",
|
||||
"mdp_core_clk";
|
||||
vddio-supply = <&L9B>;
|
||||
vci-supply = <&L19B>;
|
||||
vdd-supply = <&L3D>;
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
connectors = <&sde_dsi &smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_dp &sde_rscc>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@3 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_120hz_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
qcom,panel-roi-alignment = <540 40 40 40 1080 40>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,ulps-enabled;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* WQHD 60FPS cmd vid mode*/
|
||||
qcom,panel-roi-alignment = <720 40 720 40 720 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
timing@2 { /* FHD 60FPS cmd mode*/
|
||||
qcom,panel-roi-alignment = <540 40 540 40 540 40>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
timing@3 { /* HD 60FPS cmd mode*/
|
||||
qcom,panel-roi-alignment = <360 20 360 20 360 20>;
|
||||
qcom,partial-update-enabled = "single_roi";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,ulps-enabled;
|
||||
};
|
||||
9
qcom/display/display/crow-sde.dts
Normal file
9
qcom/display/display/crow-sde.dts
Normal file
@@ -0,0 +1,9 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "crow-sde.dtsi"
|
||||
|
||||
/ {
|
||||
qcom,msm-id = <608 0x10000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
250
qcom/display/display/crow-sde.dtsi
Normal file
250
qcom/display/display/crow-sde.dtsi
Normal file
@@ -0,0 +1,250 @@
|
||||
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-crow.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-crow.h>
|
||||
#include <dt-bindings/interconnect/qcom,crow.h>
|
||||
#include <dt-bindings/clock/qcom,rpmh.h>
|
||||
#include <dt-bindings/clock/qcom,tcsrcc-kalama.h>
|
||||
#include "crow-sde-common.dtsi"
|
||||
|
||||
&soc {
|
||||
ext_disp: qcom,msm-ext-disp {
|
||||
compatible = "qcom,msm-ext-disp";
|
||||
|
||||
ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
|
||||
compatible = "qcom,msm-ext-disp-audio-codec-rx";
|
||||
};
|
||||
};
|
||||
|
||||
qcom_msmhdcp: qcom,msm_hdcp {
|
||||
compatible = "qcom,msm-hdcp";
|
||||
};
|
||||
|
||||
sde_dp: qcom,dp_display@ae90000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,dp-display";
|
||||
|
||||
usb-phy = <&usb_qmp_dp_phy>;
|
||||
qcom,ext-disp = <&ext_disp>;
|
||||
qcom,altmode-dev = <&altmode 0>;
|
||||
usb-controller = <&usb0>;
|
||||
|
||||
reg = <0xae90000 0x0fc>,
|
||||
<0xae90200 0x0c0>,
|
||||
<0xae90400 0x770>,
|
||||
<0xae91000 0x098>,
|
||||
<0x88eaa00 0x200>,
|
||||
<0x88ea200 0x200>,
|
||||
<0x88ea600 0x200>,
|
||||
<0x88ea000 0x200>,
|
||||
<0x88e8000 0x20>,
|
||||
<0x0aee1000 0x034>,
|
||||
<0xae91400 0x098>,
|
||||
<0xaf09000 0x14>;
|
||||
reg-names = "dp_ahb", "dp_aux", "dp_link",
|
||||
"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
|
||||
"dp_pll", "usb3_dp_com", "hdcp_physical",
|
||||
"dp_p1", "gdsc";
|
||||
|
||||
interrupt-parent = <&mdss_mdp>;
|
||||
interrupts = <12 0>;
|
||||
|
||||
#clock-cells = <1>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>,
|
||||
<&tcsrcc TCSR_USB3_CLKREF_EN>,
|
||||
<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
||||
<&sde_dp 0>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
|
||||
<&sde_dp 1>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
|
||||
clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src",
|
||||
"core_usb_pipe_clk", "link_clk", "link_clk_src", "link_iface_clk",
|
||||
"link_parent", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg",
|
||||
"strm0_pixel_clk", "strm1_pixel_clk";
|
||||
|
||||
qcom,pll-revision = "4nm-v1";
|
||||
qcom,phy-version = <0x600>;
|
||||
qcom,aux-cfg0-settings = [20 00];
|
||||
qcom,aux-cfg1-settings = [24 13];
|
||||
qcom,aux-cfg2-settings = [28 A4];
|
||||
qcom,aux-cfg3-settings = [2c 00];
|
||||
qcom,aux-cfg4-settings = [30 0a];
|
||||
qcom,aux-cfg5-settings = [34 26];
|
||||
qcom,aux-cfg6-settings = [38 0a];
|
||||
qcom,aux-cfg7-settings = [3c 03];
|
||||
qcom,aux-cfg8-settings = [40 b7];
|
||||
qcom,aux-cfg9-settings = [44 03];
|
||||
|
||||
qcom,max-pclk-frequency-khz = <675000>;
|
||||
|
||||
qcom,widebus-enable;
|
||||
qcom,dsc-feature-enable;
|
||||
qcom,fec-feature-enable;
|
||||
qcom,dsc-continuous-pps;
|
||||
|
||||
qcom,qos-cpu-mask = <0xf>;
|
||||
qcom,qos-cpu-latency-us = <300>;
|
||||
|
||||
vdda-1p2-supply = <&L4B>;
|
||||
vdda-0p9-supply = <&L3B>;
|
||||
vdda_usb-0p9-supply = <&L2B>;
|
||||
vdd_mx-supply = <&VDD_MXA_LEVEL>;
|
||||
dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
|
||||
|
||||
qcom,ctrl-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,ctrl-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-1p2";
|
||||
qcom,supply-min-voltage = <1200000>;
|
||||
qcom,supply-max-voltage = <1200000>;
|
||||
qcom,supply-enable-load = <30100>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,phy-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,phy-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdda-0p9";
|
||||
qcom,supply-min-voltage = <912000>;
|
||||
qcom,supply-max-voltage = <912000>;
|
||||
qcom,supply-enable-load = <115000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
|
||||
qcom,phy-supply-entry@1 {
|
||||
reg = <1>;
|
||||
qcom,supply-name = "vdda_usb-0p9";
|
||||
qcom,supply-min-voltage = <880000>;
|
||||
qcom,supply-max-voltage = <880000>;
|
||||
qcom,supply-enable-load = <323000>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
qcom,pll-supply-entries {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
qcom,pll-supply-entry@0 {
|
||||
reg = <0>;
|
||||
qcom,supply-name = "vdd_mx";
|
||||
qcom,supply-min-voltage =
|
||||
<RPMH_REGULATOR_LEVEL_TURBO>;
|
||||
qcom,supply-max-voltage =
|
||||
<RPMH_REGULATOR_LEVEL_MAX>;
|
||||
qcom,supply-enable-load = <0>;
|
||||
qcom,supply-disable-load = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sde_rscc: qcom,sde_rscc@af20000 {
|
||||
cell-index = <0>;
|
||||
compatible = "qcom,sde-rsc";
|
||||
reg = <0xaf20000 0x4d6c>,
|
||||
<0xaf30000 0x3fd4>;
|
||||
reg-names = "drv", "wrapper";
|
||||
qcom,sde-rsc-version = <5>;
|
||||
|
||||
qcom,sde-dram-channels = <2>;
|
||||
|
||||
vdd-supply = <&disp_cc_mdss_core_gdsc>;
|
||||
clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
|
||||
clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
|
||||
|
||||
qcom,msm-bus,active-only;
|
||||
interconnects =
|
||||
<&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>;
|
||||
interconnect-names = "qcom,sde-data-bus0";
|
||||
};
|
||||
|
||||
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
|
||||
compatible = "qcom,smmu_sde_unsec";
|
||||
iommus = <&apps_smmu 0x1c00 0x2>;
|
||||
qcom,iommu-dma-addr-pool = <0x00020000 0xb7fe0000 0xbab00000 0x45500000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-earlymap; /* for cont-splash */
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
smmu_sde_sec: qcom,smmu_sde_sec_cb {
|
||||
compatible = "qcom,smmu_sde_sec";
|
||||
iommus = <&apps_smmu 0x1c01 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
qcom,iommu-vmid = <0xa>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
clocks =
|
||||
<&gcc GCC_DISP_HF_AXI_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
|
||||
clock-names = "gcc_bus",
|
||||
"iface_clk", "branch_clk", "core_clk", "vsync_clk",
|
||||
"lut_clk";
|
||||
clock-rate = <0 0 520000000 520000000 19200000 520000000>;
|
||||
clock-max-rate = <0 0 520000000 520000000 19200000 520000000>;
|
||||
|
||||
/* data and reg bus scale settings */
|
||||
interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,
|
||||
<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
|
||||
<&gem_noc MASTER_APPSS_PROC
|
||||
&config_noc SLAVE_DISPLAY_CFG>;
|
||||
interconnect-names = "qcom,sde-data-bus0",
|
||||
"qcom,sde-ebi-bus", "qcom,sde-reg-bus";
|
||||
|
||||
qcom,sde-ib-bw-vote = <2500000 0 800000>;
|
||||
qcom,sde-has-idle-pc;
|
||||
qcom,sde-dspp-ltm-version = <0x00010002>;
|
||||
/* offsets are based off dspp 0 and 1 */
|
||||
qcom,sde-dspp-ltm-off = <0x15300 0x14300>;
|
||||
};
|
||||
|
||||
&disp_rsc_drv0 {
|
||||
sde_rsc_rpmh {
|
||||
compatible = "qcom,sde-rsc-rpmh";
|
||||
cell-index = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-1p2-supply = <&L4B>;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
|
||||
<&rpmhcc RPMH_CXO_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
|
||||
};
|
||||
|
||||
&mdss_dsi_phy0 {
|
||||
vdda-0p9-supply = <&L2B>;
|
||||
qcom,panel-allow-phy-poweroff;
|
||||
qcom,dsi-pll-ssc-en;
|
||||
qcom,dsi-pll-ssc-mode = "down-spread";
|
||||
pll_codes_region = <&dsi_pll_codes_data>;
|
||||
|
||||
};
|
||||
@@ -0,0 +1,451 @@
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_120hz_cmd: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_cmd {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled cmd mode dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-color-order = "rgb_swap_rgb";
|
||||
qcom,mdss-dsi-underflow-color = <0xff>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,mdss-dsi-panel-mode-switch;
|
||||
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-lane-map = "lane_map_0123";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-te-pin-select = <1>;
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-te-dcs-command = <1>;
|
||||
qcom,mdss-dsi-te-check-enable;
|
||||
qcom,mdss-dsi-te-using-te-pin;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-cmd-mode;
|
||||
qcom,mdss-dsi-video-mode;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <706233600>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 0a e1 0a e1 0a
|
||||
81 09 92 06 c5 00 48 00 3e 00 2b 00
|
||||
0c 00 0c 05 00 3f
|
||||
];
|
||||
|
||||
qcom,cmd-on-commands = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 00
|
||||
39 01 00 00 00 00 02 6c 01
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 02 65 16
|
||||
39 01 00 00 00 00 03 EB 00 00
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 ce 0a e1 0a e1 0a
|
||||
81 09 92 06 c5 00 48 00 3e 00 2b 00
|
||||
0c 00 0c 05 00 3f
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,vid-on-commands = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 00
|
||||
39 01 00 00 00 00 02 6C 01
|
||||
39 01 00 00 00 00 02 6D 00
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 5F 70 12 00 00 AB 30
|
||||
80 09 60 04 38 00 28 02 1C 02 1C 02
|
||||
00 02 0E 00 20 03 DD 00 07 00 0C 02
|
||||
77 02 8B 18 00 10 F0 07 10 20 00 06
|
||||
0F 0F 33 0E 1C 2A 38 46 54 62 69 70
|
||||
77 79 7B 7D 7E 02 02 22 00 2A 40 2A
|
||||
BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B
|
||||
B6 4B B6 4B F4 4B F4 6C 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 F0 AA 10
|
||||
39 01 00 00 00 00 02 65 16
|
||||
39 01 00 00 00 00 03 EB 00 00
|
||||
39 01 00 00 00 00 16 B1 01 38 00 14 00
|
||||
1C 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 CC 00
|
||||
39 01 00 00 00 00 03 F0 AA 13
|
||||
39 01 00 00 00 00 18 CE 09 11 09 11 08
|
||||
C1 07 FA 05 A4 00 3C 00 34 00 24 00
|
||||
0C 00 0C 04 00 35
|
||||
39 01 00 00 00 00 03 F0 AA 14
|
||||
39 01 00 00 00 00 03 B2 03 33
|
||||
39 01 00 00 00 00 0D B4 00 33 00 00 00
|
||||
3E 00 00 00 3E 00 00
|
||||
39 01 00 00 00 00 0A B5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 B9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0D BC 10 00 00 06 11
|
||||
09 3B 09 47 09 47 00
|
||||
39 01 00 00 00 00 0D BE 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 FF 5A 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 FA 08 08 08
|
||||
39 01 00 00 00 00 03 FF 5A 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 F3 0F
|
||||
39 01 00 00 00 00 03 F0 AA 00
|
||||
39 01 00 00 00 00 03 FF 5A 82
|
||||
39 01 00 00 00 00 02 F9 00
|
||||
39 01 00 00 00 00 03 FF 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 F8 00
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 F4 9A
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,cmd-mode-switch-out-commands = [
|
||||
39 01 00 00 00 00 02 6f 07
|
||||
];
|
||||
qcom,cmd-mode-switch-out-commands-state =
|
||||
"dsi_lp_mode";
|
||||
|
||||
qcom,video-mode-switch-in-commands = [
|
||||
39 01 00 00 00 00 02 6f 01
|
||||
];
|
||||
qcom,video-mode-switch-in-commands-state =
|
||||
"dsi_lp_mode";
|
||||
|
||||
qcom,video-mode-switch-out-commands = [
|
||||
39 01 00 00 00 00 02 6f 03
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
];
|
||||
qcom,video-mode-switch-out-commands-state =
|
||||
"dsi_lp_mode";
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@1 {
|
||||
cell-index = <1>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <706233600>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 0e 81 0e 81 0e
|
||||
01 0c c3 09 06 00 60 00 53 00 3a 00
|
||||
0c 00 0c 07 00 54
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 00
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 02 65 16
|
||||
39 01 00 00 00 00 03 EB 00 00
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 cc 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 0e 81 0e 81 0e
|
||||
01 0c c3 09 06 00 60 00 53 00 3a 00
|
||||
0c 00 0c 07 00 54
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
|
||||
timing@2 {
|
||||
cell-index = <2>;
|
||||
qcom,mdss-dsi-panel-framerate = <60>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
|
||||
qcom,mdss-dsi-panel-clockrate = <706233600>;
|
||||
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 15 c2 15 c2 15
|
||||
02 13 25 0d 8a 00 90 00 7d 00 57 00
|
||||
0c 00 0c 0b 00 7e
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 00
|
||||
39 01 00 00 00 00 02 6c 02
|
||||
39 01 00 00 00 00 02 6d 00
|
||||
39 01 00 00 00 00 02 6f 02
|
||||
39 01 00 00 00 00 5f 70 12 00 00 ab 30
|
||||
80 09 60 04 38 00 28 02 1c 02 1c 02
|
||||
00 02 0e 00 20 03 dd 00 07 00 0c 02
|
||||
77 02 8b 18 00 10 f0 07 10 20 00 06
|
||||
0f 0f 33 0e 1c 2a 38 46 54 62 69 70
|
||||
77 79 7b 7d 7e 02 02 22 00 2a 40 2a
|
||||
be 3a fc 3a fa 3a f8 3b 38 3b 78 3b
|
||||
b6 4b b6 4b f4 4b f4 6c 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 f0 aa 10
|
||||
39 01 00 00 00 00 02 65 16
|
||||
39 01 00 00 00 00 03 EB 00 00
|
||||
39 01 00 00 00 00 16 b1 01 38 00 14 00
|
||||
1c 00 01 66 00 14 01 fc 00 01 66 00
|
||||
14 0d 6c 00
|
||||
39 01 00 00 00 00 03 f0 aa 13
|
||||
39 01 00 00 00 00 18 d3 15 c2 15 c2 15
|
||||
02 13 25 0d 8a 00 90 00 7d 00 57 00
|
||||
0c 00 0c 0b 00 7e
|
||||
39 01 00 00 00 00 03 f0 aa 14
|
||||
39 01 00 00 00 00 03 b2 03 33
|
||||
39 01 00 00 00 00 0d b4 00 33 00 00 00
|
||||
3e 00 00 00 3e 00 00
|
||||
39 01 00 00 00 00 0a b5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 b9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0d bc 10 00 00 06 11
|
||||
09 3b 09 47 09 47 00
|
||||
39 01 00 00 00 00 0d be 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 ff 5a 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 fa 08 08 08
|
||||
39 01 00 00 00 00 03 ff 5a 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 f3 0f
|
||||
39 01 00 00 00 00 03 f0 aa 00
|
||||
39 01 00 00 00 00 03 ff 5a 82
|
||||
39 01 00 00 00 00 02 f9 00
|
||||
39 01 00 00 00 00 03 ff 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 f8 00
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 f4 9a
|
||||
39 01 00 00 00 00 03 ff 5a 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,129 @@
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_120hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_120hz_vid {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled video mode dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <120>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 00
|
||||
39 01 00 00 00 00 02 6C 01
|
||||
39 01 00 00 00 00 02 6D 00
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 5F 70 12 00 00 AB 30
|
||||
80 09 60 04 38 00 28 02 1C 02 1C 02
|
||||
00 02 0E 00 20 03 DD 00 07 00 0C 02
|
||||
77 02 8B 18 00 10 F0 07 10 20 00 06
|
||||
0F 0F 33 0E 1C 2A 38 46 54 62 69 70
|
||||
77 79 7B 7D 7E 02 02 22 00 2A 40 2A
|
||||
BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B
|
||||
B6 4B B6 4B F4 4B F4 6C 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 F0 AA 10
|
||||
39 01 00 00 00 00 02 65 16
|
||||
39 01 00 00 00 00 03 EB 00 00
|
||||
39 01 00 00 00 00 16 B1 01 38 00 14 00
|
||||
1C 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 CC 00
|
||||
39 01 00 00 00 00 03 F0 AA 13
|
||||
39 01 00 00 00 00 18 CE 09 11 09 11 08
|
||||
C1 07 FA 05 A4 00 3C 00 34 00 24 00
|
||||
0C 00 0C 04 00 35
|
||||
39 01 00 00 00 00 03 F0 AA 14
|
||||
39 01 00 00 00 00 03 B2 03 33
|
||||
39 01 00 00 00 00 0D B4 00 33 00 00 00
|
||||
3E 00 00 00 3E 00 00
|
||||
39 01 00 00 00 00 0A B5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 B9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0D BC 10 00 00 06 11
|
||||
09 3B 09 47 09 47 00
|
||||
39 01 00 00 00 00 0D BE 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 FF 5A 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 FA 08 08 08
|
||||
39 01 00 00 00 00 03 FF 5A 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 F3 0F
|
||||
39 01 00 00 00 00 03 F0 AA 00
|
||||
39 01 00 00 00 00 03 FF 5A 82
|
||||
39 01 00 00 00 00 02 F9 00
|
||||
39 01 00 00 00 00 03 FF 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 F8 00
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 F4 9A
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,129 @@
|
||||
&mdss_mdp {
|
||||
dsi_vtdr6130_amoled_90hz_video: qcom,mdss_dsi_vtdr6130_fhd_plus_90hz_vid {
|
||||
qcom,mdss-dsi-panel-name =
|
||||
"vtdr6130 amoled video mode dsi visionox panel with DSC";
|
||||
qcom,mdss-dsi-panel-type = "dsi_video_mode";
|
||||
qcom,mdss-dsi-panel-physical-type = "oled";
|
||||
qcom,mdss-dsi-virtual-channel-id = <0>;
|
||||
qcom,mdss-dsi-stream = <0>;
|
||||
qcom,mdss-dsi-bpp = <24>;
|
||||
qcom,mdss-dsi-border-color = <0>;
|
||||
qcom,dsi-ctrl-num = <0>;
|
||||
qcom,dsi-phy-num = <0>;
|
||||
qcom,dsi-sec-ctrl-num = <1>;
|
||||
qcom,dsi-sec-phy-num = <1>;
|
||||
qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
|
||||
qcom,mdss-dsi-bllp-eof-power-mode;
|
||||
qcom,mdss-dsi-bllp-power-mode;
|
||||
qcom,mdss-dsi-lane-0-state;
|
||||
qcom,mdss-dsi-lane-1-state;
|
||||
qcom,mdss-dsi-lane-2-state;
|
||||
qcom,mdss-dsi-lane-3-state;
|
||||
qcom,mdss-dsi-dma-trigger = "trigger_sw";
|
||||
qcom,mdss-dsi-mdp-trigger = "none";
|
||||
qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
|
||||
|
||||
qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
|
||||
17000 15500 30000 8000 3000>;
|
||||
qcom,mdss-dsi-panel-peak-brightness = <4200000>;
|
||||
qcom,mdss-dsi-panel-blackness-level = <3230>;
|
||||
|
||||
qcom,mdss-dsi-wr-mem-start = <0x2c>;
|
||||
qcom,mdss-dsi-wr-mem-continue = <0x3c>;
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 {
|
||||
cell-index = <0>;
|
||||
qcom,mdss-dsi-panel-framerate = <90>;
|
||||
qcom,mdss-dsi-panel-width = <1080>;
|
||||
qcom,mdss-dsi-panel-height = <2400>;
|
||||
qcom,mdss-dsi-h-front-porch = <20>;
|
||||
qcom,mdss-dsi-h-back-porch = <20>;
|
||||
qcom,mdss-dsi-h-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-sync-skew = <0>;
|
||||
qcom,mdss-dsi-v-back-porch = <18>;
|
||||
qcom,mdss-dsi-v-front-porch = <20>;
|
||||
qcom,mdss-dsi-v-pulse-width = <2>;
|
||||
qcom,mdss-dsi-h-left-border = <0>;
|
||||
qcom,mdss-dsi-h-right-border = <0>;
|
||||
qcom,mdss-dsi-v-top-border = <0>;
|
||||
qcom,mdss-dsi-v-bottom-border = <0>;
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 02 03 01
|
||||
39 01 00 00 00 00 02 35 00
|
||||
39 01 00 00 00 00 02 53 20
|
||||
39 01 00 00 00 00 03 51 00 00
|
||||
39 01 00 00 00 00 02 59 00
|
||||
39 01 00 00 00 00 02 6C 01
|
||||
39 01 00 00 00 00 02 6D 00
|
||||
39 01 00 00 00 00 02 6F 01
|
||||
39 01 00 00 00 00 5F 70 12 00 00 AB 30
|
||||
80 09 60 04 38 00 28 02 1C 02 1C 02
|
||||
00 02 0E 00 20 03 DD 00 07 00 0C 02
|
||||
77 02 8B 18 00 10 F0 07 10 20 00 06
|
||||
0F 0F 33 0E 1C 2A 38 46 54 62 69 70
|
||||
77 79 7B 7D 7E 02 02 22 00 2A 40 2A
|
||||
BE 3A FC 3A FA 3A F8 3B 38 3B 78 3B
|
||||
B6 4B B6 4B F4 4B F4 6C 34 84 74 00
|
||||
00 00 00 00 00
|
||||
39 01 00 00 00 00 03 F0 AA 10
|
||||
39 01 00 00 00 00 02 65 16
|
||||
39 01 00 00 00 00 03 EB 00 00
|
||||
39 01 00 00 00 00 16 B1 01 38 00 14 00
|
||||
1C 00 01 66 00 14 00 14 00 01 66 00
|
||||
14 05 CC 00
|
||||
39 01 00 00 00 00 03 F0 AA 13
|
||||
39 01 00 00 00 00 18 CE 09 11 09 11 08
|
||||
C1 07 FA 05 A4 00 3C 00 34 00 24 00
|
||||
0C 00 0C 04 00 35
|
||||
39 01 00 00 00 00 03 F0 AA 14
|
||||
39 01 00 00 00 00 03 B2 03 33
|
||||
39 01 00 00 00 00 0D B4 00 33 00 00 00
|
||||
3E 00 00 00 3E 00 00
|
||||
39 01 00 00 00 00 0A B5 00 09 09 09 09
|
||||
09 09 06 01
|
||||
39 01 00 00 00 00 07 B9 00 00 08 09 09
|
||||
09
|
||||
39 01 00 00 00 00 0D BC 10 00 00 06 11
|
||||
09 3B 09 47 09 47 00
|
||||
39 01 00 00 00 00 0D BE 10 10 00 08 22
|
||||
09 19 09 25 09 25 00
|
||||
39 01 00 00 00 00 03 FF 5A 80
|
||||
39 01 00 00 00 00 02 65 14
|
||||
39 01 00 00 00 00 04 FA 08 08 08
|
||||
39 01 00 00 00 00 03 FF 5A 81
|
||||
39 01 00 00 00 00 02 65 05
|
||||
39 01 00 00 00 00 02 F3 0F
|
||||
39 01 00 00 00 00 03 F0 AA 00
|
||||
39 01 00 00 00 00 03 FF 5A 82
|
||||
39 01 00 00 00 00 02 F9 00
|
||||
39 01 00 00 00 00 03 FF 51 83
|
||||
39 01 00 00 00 00 02 65 04
|
||||
39 01 00 00 00 00 02 F8 00
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
39 01 00 00 00 00 02 65 01
|
||||
39 01 00 00 00 00 02 F4 9A
|
||||
39 01 00 00 00 00 03 FF 5A 00
|
||||
05 01 00 00 78 00 01 11
|
||||
05 01 00 00 14 00 01 29
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 14 00 02 28 00
|
||||
05 01 00 00 78 00 02 10 00];
|
||||
qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
|
||||
qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
|
||||
qcom,mdss-dsi-timing-switch-command-state =
|
||||
"dsi_lp_mode";
|
||||
qcom,mdss-dsi-h-sync-pulse = <0>;
|
||||
qcom,compression-mode = "dsc";
|
||||
qcom,mdss-dsc-slice-height = <40>;
|
||||
qcom,mdss-dsc-slice-width = <540>;
|
||||
qcom,mdss-dsc-slice-per-pkt = <1>;
|
||||
qcom,mdss-dsc-bit-per-component = <8>;
|
||||
qcom,mdss-dsc-bit-per-pixel = <8>;
|
||||
qcom,mdss-dsc-block-prediction-enable;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -154,7 +154,7 @@
|
||||
qcom,sde-mixer-blendstages = <0xb>;
|
||||
qcom,sde-highest-bank-bit = <0x8 0x3>,
|
||||
<0x7 0x2>;
|
||||
qcom,sde-ubwc-version = <0x40000002>;
|
||||
qcom,sde-ubwc-version = <0x40030001>;
|
||||
qcom,sde-ubwc-swizzle = <0x6>;
|
||||
qcom,sde-ubwc-bw-calc-version = <0x1>;
|
||||
qcom,sde-ubwc-static = <0x1>;
|
||||
@@ -230,6 +230,7 @@
|
||||
qcom,sde-qos-cpu-irq-latency = <300>;
|
||||
|
||||
qcom,sde-ipcc-protocol-id = <0x2>;
|
||||
qcom,sde-ipcc-client-dpu-phys-id = <0x19>;
|
||||
|
||||
/* offsets are relative to "mdp_phys + qcom,sde-off */
|
||||
qcom,sde-reg-dma-off = <0 0x400>;
|
||||
|
||||
@@ -6,6 +6,7 @@
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama CDP ST54K NFC";
|
||||
compatible = "qcom,kalama-cdp", "qcom,kalama", "qcom,cdp";
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>;
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>,
|
||||
<603 0x20000>, <604 0x20000>;
|
||||
qcom,board-id = <0x02010001 0>;
|
||||
};
|
||||
|
||||
@@ -6,6 +6,7 @@
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama CDP";
|
||||
compatible = "qcom,kalama-cdp", "qcom,kalama", "qcom,cdp";
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>;
|
||||
qcom,board-id = <0x10001 0>;
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>,
|
||||
<603 0x20000>, <604 0x20000>;
|
||||
qcom,board-id = <0x10001 0>, <0x03010001 0x3>;
|
||||
};
|
||||
|
||||
@@ -6,6 +6,7 @@
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama CDP - WSA883X";
|
||||
compatible = "qcom,kalama-cdp", "qcom,kalama", "qcom,cdp";
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>;
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>,
|
||||
<603 0x20000>, <604 0x20000>;
|
||||
qcom,board-id = <0x1010001 0>;
|
||||
};
|
||||
|
||||
@@ -178,7 +178,7 @@
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
qcom,bl-dcs-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
|
||||
@@ -436,6 +436,11 @@
|
||||
|
||||
&dsi_sharp_qhd_plus_dsc_video {
|
||||
qcom,dsi-select-clocks = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
|
||||
qcom,dsi-supported-dfps-list = <120 90 60>;
|
||||
qcom,mdss-dsi-pan-enable-dynamic-fps;
|
||||
qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
|
||||
|
||||
qcom,mdss-dsi-display-timings {
|
||||
timing@0 { /* 120 FPS */
|
||||
qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 16 21 07
|
||||
|
||||
@@ -5,7 +5,8 @@
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama HDK";
|
||||
compatible = "qcom,kalama-hdk", "qcom,kalama", "qcom,hdk";
|
||||
qcom,msm-id = <536 0x10000>, <536 0x20000>;
|
||||
compatible = "qcom,kalama-hdk", "qcom,kalama", "qcom,hdk",
|
||||
"qcom,kalamap";
|
||||
qcom,msm-id = <536 0x10000>, <536 0x20000>, <603 0x20000>;
|
||||
qcom,board-id = <0x1001f 0>;
|
||||
};
|
||||
|
||||
@@ -80,7 +80,7 @@
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
qcom,bl-dcs-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
|
||||
@@ -158,7 +158,7 @@
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
qcom,bl-dcs-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
|
||||
@@ -6,6 +6,7 @@
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama MTP ST54K NFC";
|
||||
compatible = "qcom,kalama-mtp", "qcom,kalama", "qcom,mtp";
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>;
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>,
|
||||
<604 0x20000>;
|
||||
qcom,board-id = <0x1010008 0>;
|
||||
};
|
||||
|
||||
@@ -6,6 +6,7 @@
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama MTP";
|
||||
compatible = "qcom,kalama-mtp", "qcom,kalama", "qcom,mtp";
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>;
|
||||
qcom,board-id = <0x10008 0>;
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>,
|
||||
<604 0x20000>;
|
||||
qcom,board-id = <0x10008 0>, <0x02010008 0x2>;
|
||||
};
|
||||
|
||||
@@ -158,7 +158,7 @@
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
qcom,bl-dcs-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
|
||||
@@ -158,7 +158,7 @@
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
qcom,bl-dcs-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
|
||||
@@ -6,6 +6,7 @@
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Kalama RCM";
|
||||
compatible = "qcom,kalama-rcm", "qcom,kalama", "qcom,rcm";
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>, <536 0x20000>;
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>, <519 0x20000>,
|
||||
<536 0x20000>, <603 0x20000>, <604 0x20000>;
|
||||
qcom,board-id = <0x10015 0>;
|
||||
};
|
||||
|
||||
@@ -4,6 +4,7 @@
|
||||
#include "kalama-sde.dtsi"
|
||||
|
||||
/ {
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>;
|
||||
qcom,msm-id = <519 0x10000>, <536 0x10000>,
|
||||
<603 0x20000>, <604 0x20000>;
|
||||
qcom,board-id = <0 0>;
|
||||
};
|
||||
|
||||
@@ -57,6 +57,7 @@
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
|
||||
<&sde_dp 0>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
|
||||
<&sde_dp 1>,
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
|
||||
@@ -64,7 +65,7 @@
|
||||
<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
|
||||
clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src",
|
||||
"core_usb_pipe_clk", "link_clk", "link_clk_src", "link_iface_clk",
|
||||
"pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg",
|
||||
"link_parent", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg",
|
||||
"strm0_pixel_clk", "strm1_pixel_clk";
|
||||
|
||||
qcom,pll-revision = "4nm-v1.1";
|
||||
@@ -250,7 +251,7 @@
|
||||
|
||||
&mdss_dsi0 {
|
||||
vdda-1p2-supply = <&L3E>;
|
||||
qcom,split-link-supported;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
@@ -264,7 +265,7 @@
|
||||
|
||||
&mdss_dsi1 {
|
||||
vdda-1p2-supply = <&L3E>;
|
||||
qcom,split-link-supported;
|
||||
|
||||
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
|
||||
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
|
||||
|
||||
@@ -0,0 +1,12 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-crow-sde.dtsi"
|
||||
#include "trustedvm-crow-sde-display-atp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Crow ATP - TrustedVM";
|
||||
compatible = "qcom,crow-atp", "qcom,crow", "qcom,atp";
|
||||
qcom,msm-id = <608 0x10000>;
|
||||
qcom,board-id = <33 0>;
|
||||
};
|
||||
1
qcom/display/display/trustedvm-crow-sde-display-atp.dtsi
Normal file
1
qcom/display/display/trustedvm-crow-sde-display-atp.dtsi
Normal file
@@ -0,0 +1 @@
|
||||
#include "trustedvm-crow-sde-display-idp.dtsi"
|
||||
@@ -0,0 +1,12 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-crow-sde.dtsi"
|
||||
#include "trustedvm-crow-sde-display-idp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Crow IDP - TrustedVM";
|
||||
compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp";
|
||||
qcom,msm-id = <608 0x10000>;
|
||||
qcom,board-id = <34 0>;
|
||||
};
|
||||
@@ -0,0 +1,12 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-crow-sde.dtsi"
|
||||
#include "trustedvm-crow-sde-display-idp-wcd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Crow IDP WCD - TrustedVM";
|
||||
compatible = "qcom,crow-idp", "qcom,crow", "qcom,idp";
|
||||
qcom,msm-id = <608 0x10000>;
|
||||
qcom,board-id = <34 1>, <34 2>, <34 3>;
|
||||
};
|
||||
@@ -0,0 +1 @@
|
||||
#include "trustedvm-crow-sde-display-idp.dtsi"
|
||||
55
qcom/display/display/trustedvm-crow-sde-display-idp.dtsi
Normal file
55
qcom/display/display/trustedvm-crow-sde-display-idp.dtsi
Normal file
@@ -0,0 +1,55 @@
|
||||
#include "trustedvm-crow-sde-display.dtsi"
|
||||
|
||||
&dsi_vtdr6130_amoled_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_vtdr6130_amoled_qsync_144hz_video {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,mdss-dsi-bl-min-level = <10>;
|
||||
qcom,mdss-dsi-bl-max-level = <4095>;
|
||||
qcom,mdss-brightness-max-level = <8191>;
|
||||
qcom,mdss-dsi-bl-inverted-dbv;
|
||||
qcom,platform-reset-gpio = <&tlmm 29 0>;
|
||||
};
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_375_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_dsc_10b_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>;
|
||||
};
|
||||
@@ -0,0 +1,12 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-crow-sde.dtsi"
|
||||
#include "trustedvm-crow-sde-display-qrd.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Crow QRD - TrustedVM";
|
||||
compatible = "qcom,crow-qrd", "qcom,crow", "qcom,qrd";
|
||||
qcom,msm-id = <608 0x10000>;
|
||||
qcom,board-id = <11 0>;
|
||||
};
|
||||
5
qcom/display/display/trustedvm-crow-sde-display-qrd.dtsi
Normal file
5
qcom/display/display/trustedvm-crow-sde-display-qrd.dtsi
Normal file
@@ -0,0 +1,5 @@
|
||||
#include "trustedvm-crow-sde-display-idp.dtsi"
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_vtdr6130_amoled_cmd>;
|
||||
};
|
||||
@@ -0,0 +1,12 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include "trustedvm-crow-sde.dtsi"
|
||||
#include "trustedvm-crow-sde-display-rumi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. Crow RUMI - TrustedVM";
|
||||
compatible = "qcom,crow-rumi", "qcom,crow", "qcom,rumi";
|
||||
qcom,msm-id = <608 0x10000>;
|
||||
qcom,board-id = <15 0>;
|
||||
};
|
||||
13
qcom/display/display/trustedvm-crow-sde-display-rumi.dtsi
Normal file
13
qcom/display/display/trustedvm-crow-sde-display-rumi.dtsi
Normal file
@@ -0,0 +1,13 @@
|
||||
#include "trustedvm-crow-sde-display.dtsi"
|
||||
|
||||
&dsi_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&dsi_sim_vid {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
};
|
||||
|
||||
&sde_dsi {
|
||||
qcom,dsi-default-panel = <&dsi_sim_vid>;
|
||||
};
|
||||
12
qcom/display/display/trustedvm-crow-sde-display.dtsi
Normal file
12
qcom/display/display/trustedvm-crow-sde-display.dtsi
Normal file
@@ -0,0 +1,12 @@
|
||||
#include "crow-sde-display-common.dtsi"
|
||||
|
||||
&sde_dsi {
|
||||
clocks = <&clock_cpucc 0>,
|
||||
<&clock_cpucc 1>;
|
||||
clock-names = "pll_byte_clk0", "pll_dsi_clk0";
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
connectors = <&sde_dsi &smmu_sde_unsec>;
|
||||
};
|
||||
|
||||
64
qcom/display/display/trustedvm-crow-sde.dtsi
Normal file
64
qcom/display/display/trustedvm-crow-sde.dtsi
Normal file
@@ -0,0 +1,64 @@
|
||||
#include <dt-bindings/clock/qcom,gcc-crow.h>
|
||||
#include <dt-bindings/clock/qcom,dispcc-crow.h>
|
||||
#include "crow-sde-common.dtsi"
|
||||
|
||||
&soc {
|
||||
/* dummy display clock provider */
|
||||
clock_cpucc: qcom,cpucc {
|
||||
compatible = "qcom,dummycc";
|
||||
clock-output-names = "cpucc_clocks";
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
|
||||
compatible = "qcom,smmu_sde_unsec";
|
||||
iommus = <&apps_smmu 0x1c04 0x2>,
|
||||
<&apps_smmu 0x1c03 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
|
||||
qcom,iommu-faults = "non-fatal";
|
||||
dma-coherent;
|
||||
};
|
||||
};
|
||||
|
||||
&mdss_mdp {
|
||||
reg = <0x0ae00000 0x84000>,
|
||||
<0x0aeb0000 0x2008>,
|
||||
<0x0aeac000 0x800>,
|
||||
<0x0ae8f000 0x02c>;
|
||||
|
||||
reg-names = "mdp_phys",
|
||||
"vbif_phys",
|
||||
"regdma_phys",
|
||||
"sid_phys";
|
||||
|
||||
qcom,sde-vm-exclude-reg-names = "sid_phys";
|
||||
qcom,tvm-include-reg = <0xaf20000 0x4d6c>,
|
||||
<0xaf30000 0x3fd4>;
|
||||
|
||||
qcom,sde-hw-version =<0x90060000>;
|
||||
|
||||
clocks = <&clock_cpucc GCC_DISP_HF_AXI_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_MDP_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>;
|
||||
clock-names = "gcc_bus", "iface_clk", "branch_clk",
|
||||
"core_clk", "vsync_clk", "lut_clk";
|
||||
qcom,sde-trusted-vm-env;
|
||||
};
|
||||
|
||||
&mdss_dsi0 {
|
||||
clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
|
||||
<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
|
||||
<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
|
||||
clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
|
||||
"pixel_clk", "pixel_clk_rcg", "esc_clk";
|
||||
};
|
||||
|
||||
&mdss_dsi_phy0 {
|
||||
qcom,dsi-pll-in-trusted-vm;
|
||||
};
|
||||
@@ -135,7 +135,7 @@
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
qcom,bl-dcs-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
|
||||
@@ -116,7 +116,7 @@
|
||||
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
qcom,bl-dcs-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_dsc_375_cmd {
|
||||
|
||||
@@ -100,7 +100,7 @@
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 0 0>;
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
qcom,bl-dcs-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
|
||||
@@ -198,7 +198,7 @@
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
qcom,bl-dcs-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
|
||||
@@ -180,7 +180,7 @@
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
qcom,bl-dcs-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
|
||||
@@ -170,7 +170,7 @@
|
||||
&dsi_dual_sim_cmd {
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply_sim>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
qcom,bl-dcs-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
|
||||
@@ -140,7 +140,7 @@
|
||||
qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
|
||||
qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
|
||||
qcom,platform-reset-gpio = <&tlmm 0 0>;
|
||||
qcom,bl-dsc-cmd-state = "dsi_lp_mode";
|
||||
qcom,bl-dcs-cmd-state = "dsi_lp_mode";
|
||||
};
|
||||
|
||||
&dsi_dual_sim_vid {
|
||||
|
||||
Reference in New Issue
Block a user