Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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Merge "ARM: dts: msm: Change cpu enable method to psci"

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qctecmdr
2022-02-09 10:52:08 -08:00
committed by Gerrit - the friendly Code Review server
parent 02d10c4f63 f79a0a8067
commit b2acbf2b17
1 changed files with 9 additions and 8 deletions
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17
qcom/cinder.dtsi
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@@ -28,8 +28,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x80C40000>;
enable-method = "psci";
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
@@ -47,8 +46,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x80C40000>;
enable-method = "psci";
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
@@ -62,8 +60,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x80C40000>;
enable-method = "psci";
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
@@ -76,8 +73,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x80C40000>;
enable-method = "psci";
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
@@ -119,6 +115,11 @@
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
intc: interrupt-controller@17200000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;