Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
2
0
Fork 0
mirror of https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees synced 2026-02-01 09:04:24 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge "ARM: dts: msm: Update GCC node for sdxpinn platform"

Browse Source
This commit is contained in:
qctecmdr
2022-10-01 19:38:57 -07:00
committed by Gerrit - the friendly Code Review server
parent d0141c3132 5c8a2d04ac
commit b51353a4df
2 changed files with 77 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
qcom/sdxpinn-rumi.dtsi
View File

@@ -221,8 +221,11 @@
};
&gcc {
clocks = <&bi_tcxo>, <&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>,
<&pcie_pipe_clk>, <&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clocks = <&bi_tcxo>, <&emac0_sgmiiphy_mac_rclk>, <&emac0_sgmiiphy_mac_tclk>,
<&emac0_sgmiiphy_rclk>, <&emac0_sgmiiphy_tclk>, <&emac1_sgmiiphy_mac_rclk>,
<&emac1_sgmiiphy_mac_tclk>, <&emac1_sgmiiphy_rclk>, <&emac1_sgmiiphy_tclk>,
<&pcie20_phy_aux_clk>, <&pcie_1_pipe_clk>, <&pcie_2_pipe_clk>, <&pcie_pipe_clk>,
<&sleep_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
};
&gcc_emac0_gdsc {

72
qcom/sdxpinn.dtsi
View File

@@ -506,6 +506,62 @@
#clock-cells = <0>;
};
emac0_sgmiiphy_mac_rclk: emac0_sgmiiphy_mac_rclk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "emac0_sgmiiphy_mac_rclk";
#clock-cells = <0>;
};
emac0_sgmiiphy_mac_tclk: emac0_sgmiiphy_mac_tclk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "emac0_sgmiiphy_mac_tclk";
#clock-cells = <0>;
};
emac0_sgmiiphy_rclk: emac0_sgmiiphy_rclk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "emac0_sgmiiphy_rclk";
#clock-cells = <0>;
};
emac0_sgmiiphy_tclk: emac0_sgmiiphy_tclk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "emac0_sgmiiphy_tclk";
#clock-cells = <0>;
};
emac1_sgmiiphy_mac_rclk: emac1_sgmiiphy_mac_rclk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "emac1_sgmiiphy_mac_rclk";
#clock-cells = <0>;
};
emac1_sgmiiphy_mac_tclk: emac1_sgmiiphy_mac_tclk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "emac1_sgmiiphy_mac_tclk";
#clock-cells = <0>;
};
emac1_sgmiiphy_rclk: emac1_sgmiiphy_rclk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "emac1_sgmiiphy_rclk";
#clock-cells = <0>;
};
emac1_sgmiiphy_tclk: emac1_sgmiiphy_tclk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "emac1_sgmiiphy_tclk";
#clock-cells = <0>;
};
pcie20_phy_aux_clk: pcie20_phy_aux_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
@@ -549,6 +605,14 @@
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&emac0_sgmiiphy_mac_rclk>,
<&emac0_sgmiiphy_mac_tclk>,
<&emac0_sgmiiphy_rclk>,
<&emac0_sgmiiphy_tclk>,
<&emac1_sgmiiphy_mac_rclk>,
<&emac1_sgmiiphy_mac_tclk>,
<&emac1_sgmiiphy_rclk>,
<&emac1_sgmiiphy_tclk>,
<&pcie20_phy_aux_clk>,
<&pcie_1_pipe_clk>,
<&pcie_2_pipe_clk>,
@@ -556,6 +620,14 @@
<&sleep_clk>,
<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
clock-names = "bi_tcxo",
"emac0_sgmiiphy_mac_rclk",
"emac0_sgmiiphy_mac_tclk",
"emac0_sgmiiphy_rclk",
"emac0_sgmiiphy_tclk",
"emac1_sgmiiphy_mac_rclk",
"emac1_sgmiiphy_mac_tclk",
"emac1_sgmiiphy_rclk",
"emac1_sgmiiphy_tclk",
"pcie20_phy_aux_clk",
"pcie_1_pipe_clk",
"pcie_2_pipe_clk",