Merge "ARM: dts: msm: Update freq-domain-cells property"

This commit is contained in:
qctecmdr
2022-08-24 16:58:15 -07:00
committed by Gerrit - the friendly Code Review server

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@@ -41,7 +41,7 @@
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
qcom,freq-domain = <&cpufreq_hw 0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
#cooling-cells = <2>;
L2_0: l2-cache {
@@ -68,7 +68,7 @@
i-cache-size = <0x8000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -90,7 +90,7 @@
i-cache-size = <0x8000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -112,7 +112,7 @@
i-cache-size = <0x8000>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>;
qcom,lmh-dcvs = <&lmh_dcvs0>;
@@ -898,7 +898,7 @@
clock-names = "xo", "alternate";
qcom,no-accumulative-counter;
qcom,max-lut-entries = <12>;
#freq-domain-cells = <2>;
#freq-domain-cells = <1>;
};
qcom,cpufreq-hw-debug@f521000 {